loadpatents
name:-0.0053780078887939
name:-0.015916109085083
name:-0.001147985458374
ViAsic, Inc. Patent Filings

ViAsic, Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for ViAsic, Inc..The latest application filed is for "logic array devices having complex macro-cell architecture and methods facilitating use of same".

Company Profile
0.14.4
  • ViAsic, Inc. - Durham NC
  • ViASIC, Inc. - Winston-Salem NC
  • VIASIC, INC. - 6015 Fayetteville Road Suite 214 Durham NC
  • ViASIC, Inc. - Chapel Hill NC
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Via configurable architecture for customization of analog circuitry in a semiconductor device
Grant 7,972,907 - Kemerling , et al. July 5, 2
2011-07-05
Using selectable in-line inverters to reduce the number of inverters in a semiconductor design
Grant 7,930,670 - Cox April 19, 2
2011-04-19
Configuring structured ASIC fabric using two non-adjacent via layers
Grant 7,692,309 - Cox April 6, 2
2010-04-06
Via configurable architecture for customization of analog circuitry in a semiconductor device
Grant 7,626,272 - Kemerling , et al. December 1, 2
2009-12-01
Configurable integrated circuit capacitor array using via mask layers
Grant 7,595,229 - Ihme , et al. September 29, 2
2009-09-29
Logic Array Devices Having Complex Macro-cell Architecture And Methods Facilitating Use Of Same
App 20090210848 - COX; William D.
2009-08-20
Logic array devices having complex macro-cell architecture and methods facilitating use of same
Grant 7,538,580 - Cox May 26, 2
2009-05-26
Configuring Structured Asic Fabric Using Two Non-adjacent Via Layers
App 20090065813 - COX; William D.
2009-03-12
VIA configurable architecture for customization of analog circuitry in a semiconductor device
Grant 7,449,371 - Kemerling , et al. November 11, 2
2008-11-11
Creating high-drive logic devices from standard gates with minimal use of custom masks
Grant 7,378,874 - Bharath , et al. May 27, 2
2008-05-27
Creating High-drive Logic Devices From Standard Gates With Minimal Use Of Custom Masks
App 20080054939 - BHARATH; Bhaskar ;   et al.
2008-03-06
Configurable integrated circuit capacitor array using via mask layers
Grant 7,335,966 - Ihme , et al. February 26, 2
2008-02-26
Customization of structured ASIC devices using pre-process extraction of routing information
Grant 7,334,208 - Cox February 19, 2
2008-02-19
Logic Array Devices Having Complex Macro-cell Architecture And Methods Facilitating Use Of Same
App 20070262789 - COX; William D.
2007-11-15
Logic array devices having complex macro-cell architecture and methods facilitating use of same
Grant 7,248,071 - Cox July 24, 2
2007-07-24
Logic array devices having complex macro-cell architecture and methods facilitating use of same
Grant 6,873,185 - Cox March 29, 2
2005-03-29
Distributed RAM in a logic array
Grant 6,693,454 - Cox February 17, 2
2004-02-17
Cell architecture to reduce customization in a semiconductor device
Grant 6,580,289 - Cox June 17, 2
2003-06-17
Company Registrations

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed