Verwegen; Peter
Patent Applications and Registrations
Patent applications and USPTO patent grants for Verwegen; Peter.The latest application filed is for "optimization of integrated circuit physical design".
- Verwegen; Peter - Rottenburg DE
| Patent | Date |
|---|---|
| Optimization of integrated circuit physical design Grant 9,536,030 - Fricke , et al. January 3, 2 | 2017-01-03 |
| Optimization Of Integrated Circuit Physical Design App 20150363531 - Fricke; Niels ; et al. | 2015-12-17 |
| Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility Grant 7,560,964 - Lackey , et al. July 14, 2 | 2009-07-14 |
| Latch and clock structures for enabling race-reduced mux scan and LSSD co-compatibility Grant 7,482,851 - Lackey , et al. January 27, 2 | 2009-01-27 |
| Edge-triggered master + LSSD slave binary latch Grant 7,401,278 - Verwegen July 15, 2 | 2008-07-15 |
| Latch And Clock Structures For Enabling Race-reduced Mux Scan And Lssd Co-compatibility App 20080042712 - LACKEY; David E. ; et al. | 2008-02-21 |
| Latch and clock structures for enabling race-reduced MUX scan and LSSD co-compatibility App 20060208783 - Lackey; David E. ; et al. | 2006-09-21 |
| Edge-triggered Master + Lssd Slave Binary Latch App 20050216806 - Verwegen, Peter | 2005-09-29 |
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