loadpatents
name:-0.0046958923339844
name:-0.010740995407104
name:-0.00040483474731445
Verret; Douglas P. Patent Filings

Verret; Douglas P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Verret; Douglas P..The latest application filed is for "well resistors and polysilicon resistors".

Company Profile
0.11.3
  • Verret; Douglas P. - Sugarland TX
  • VERRET, DOUGLAS P - FORT BEND COUNTY TX
  • Verret; Douglas P. - Sugar Land TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Well resistors and polysilicon resistors
Grant 9,379,176 - Heinrich-Barna , et al. June 28, 2
2016-06-28
Well Resistors And Polysilicon Resistors
App 20160056227 - Heinrich-Barna; Stephen Keith ;   et al.
2016-02-25
Well Resistors And Polysilicon Resistors
App 20150349046 - Heinrich-Barna; Stephen Keith ;   et al.
2015-12-03
Well resistors and polysilicon resistors
Grant 9,202,859 - Heinrich-Barna , et al. December 1, 2
2015-12-01
Method For Fabricating Narrow Metal Interconnects In An Integrated Circuit Using Heat And Pressure To Extrude A Metal Layer Into A Lead Trench And Via/contact
App 20010055840 - VERRET, DOUGLAS P
2001-12-27
Method for making very shallow junctions in silicon devices
Grant 6,130,144 - Verret October 10, 2
2000-10-10
Process for simultaneously fabricating isolation structures for bipolar and CMOS circuits
Grant 5,298,450 - Verret March 29, 1
1994-03-29
Self-aligned tungsten-filled via
Grant 5,212,352 - Brighton , et al. May 18, 1
1993-05-18
Method for forming a germanium layer and a heterojunction bipolar transistor
Grant 5,089,428 - Verret , et al. February 18, 1
1992-02-18
Metal contacts and interconnections for VLSI devices
Grant 4,843,453 - Hooper , et al. June 27, 1
1989-06-27
Bipolar transistor in isolation well with angled corners
Grant 4,799,099 - Verret , et al. January 17, 1
1989-01-17
Method of making a merge bipolar and complementary metal oxide semiconductor transistor device
Grant 4,797,372 - Verret , et al. January 10, 1
1989-01-10
Method of making metal contacts and interconnections for VLSI devices with copper as a primary conductor
Grant 4,742,014 - Hooper , et al. May 3, 1
1988-05-03
Method of plating an interconnect metal onto a metal in VLSI devices
Grant 4,619,887 - Hooper , et al. October 28, 1
1986-10-28

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