Verma; Vani

Patent Applications and Registrations

Patent applications and USPTO patent grants for Verma; Vani.The latest application filed is for "two-sided die in a four-sided leadframe based package".

Company Profile

0.13.7

Verma; Vani - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Two-sided Die In A Four-sided Leadframe Based Package App 20130200507 - Yu; Cheemen ; et al.	2013-08-08
Two-sided die in a four-sided leadframe based package Grant 8,395,246 - Yu , et al. March 12, 2	2013-03-12
Method of fabricating a two-sided die in a four-sided leadframe based package Grant 8,349,655 - Yu , et al. January 8, 2	2013-01-08
Method of fabricating a two-sided die in a four-sided leadframe based package Grant 8,058,099 - Yu , et al. November 15, 2	2011-11-15
Method Of Fabricating A Two-sided Die In A Four-sided Leadframe Based Package App 20100255640 - Yu; Cheemen ; et al.	2010-10-07
Method Of Fabricating A Two-sided Die In A Four-sided Leadframe Based Package App 20090004782 - Yu; Cheemen ; et al.	2009-01-01
Two-sided Die In A Four-sided Leadframe Based Package App 20090001534 - Yu; Cheemen ; et al.	2009-01-01
Memory module having interconnected and stacked integrated circuits Grant 7,432,599 - Verma , et al. October 7, 2	2008-10-07
Non-stick detection method and mechanism for array molded laminate packages Grant 7,391,104 - Chang , et al. June 24, 2	2008-06-24
Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process Grant 7,105,377 - Chang , et al. September 12, 2	2006-09-12
Memory module having interconnected and stacked integrated circuits App 20060118927 - Verma; Vani ; et al.	2006-06-08
Memory module having interconnected and stacked integrated circuits Grant 7,005,730 - Verma , et al. February 28, 2	2006-02-28
Non-stick detection method and mechanism for array molded laminate packages Grant 6,853,202 - Chang , et al. February 8, 2	2005-02-08
Memory module having interconnected and stacked integrated circuits App 20040169285 - Verma, Vani ; et al.	2004-09-02
Method and system for universal packaging in conjunction with a back-end integrated circuit manufacturing process Grant 6,730,532 - Chang , et al. May 4, 2	2004-05-04
Memory module having interconnected and stacked integrated circuits Grant 6,731,011 - Verma , et al. May 4, 2	2004-05-04
Memory module having interconnected and stacked integrated circuits App 20030155659 - Verma, Vani ; et al.	2003-08-21
Methods for producing high reliability lead frame and packaging semiconductor die using such lead frame Grant 6,576,491 - Chang , et al. June 10, 2	2003-06-10
High reliability lead frame and packaging technology containing the same Grant 6,331,728 - Chang , et al. December 18, 2	2001-12-18

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