loadpatents
name:-0.017755031585693
name:-0.029659986495972
name:-0.0050408840179443
Verma; Hare K. Patent Filings

Verma; Hare K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Verma; Hare K..The latest application filed is for "integrated circuits and methods to accelerate data queries".

Company Profile
4.27.15
  • Verma; Hare K. - San Jose CA
  • Verma; Hare K. - Fremont CA
  • Verma; Hare K. - Cupertino CA US
  • Verma; Hare K. - Bangalore IN
  • Verma; Hare K - Bangalore IN
  • Verma; Hare K. - Campbell CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Configurable overlay on wide memory channels for efficient memory access
Grant 10,990,517 - Verma , et al. April 27, 2
2021-04-27
Integrated circuits and methods to accelerate data queries
Grant 10,963,460 - Verma , et al. March 30, 2
2021-03-30
Integrated Circuits And Methods To Accelerate Data Queries
App 20200183937 - Verma; Hare K. ;   et al.
2020-06-11
Parallel Compute Offload To Database Accelerator
App 20180373760 - Verma; Hare K. ;   et al.
2018-12-27
Programmable logic systems and methods employing configurable floating point units
Grant 8,429,214 - Verma , et al. April 23, 2
2013-04-23
Method and apparatus for compression of configuration bitstream of field programmable logic
Grant 8,085,603 - Gunwani , et al. December 27, 2
2011-12-27
Method And Apparatus For Compression Of Configuration Bitstream Of Field Programmable Logic
App 20110058431 - Gunwani; Manoj ;   et al.
2011-03-10
Programmable Logic Systems and Methods Employing Configurable Floating Point Units
App 20110010406 - Verma; Hare K. ;   et al.
2011-01-13
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,836,113 - Sunkavalli , et al. November 16, 2
2010-11-16
Programmable logic systems and methods employing configurable floating point units
Grant 7,814,136 - Verma , et al. October 12, 2
2010-10-12
Field programmable application specific integrated circuit with programmable logic array and method of designing and programming the programmable logic array
Grant 7,800,404 - Verma , et al. September 21, 2
2010-09-21
Programmable logic cells with local connections
Grant 7,728,623 - Verma , et al. June 1, 2
2010-06-01
Programmable logic cells with local connections
Grant 7,605,605 - Verma , et al. October 20, 2
2009-10-20
Field programmable application specific integrated circuit with programmable logic array and method of designing and programming the programmable logic array
App 20090160483 - Verma; Hare K. ;   et al.
2009-06-25
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,439,768 - Sunkavalli , et al. October 21, 2
2008-10-21
Programmable function generator and method operating as combinational, sequential and routing cells
Grant 7,417,455 - Verma , et al. August 26, 2
2008-08-26
Dedicated logic cells employing sequential logic and control logic functions
Grant 7,417,456 - Verma , et al. August 26, 2
2008-08-26
Dedicated logic cells employing sequential logic and control logic functions
Grant 7,414,432 - Verma , et al. August 19, 2
2008-08-19
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,414,431 - Verma , et al. August 19, 2
2008-08-19
Dedicated logic cells employing sequential logic and control logic functions
Grant 7,368,941 - Verma , et al. May 6, 2
2008-05-06
Dedicated logic cells employing configurable logic and dedicated logic functions
Grant 7,358,765 - Verma , et al. April 15, 2
2008-04-15
Dedicated Logic Cells Employing Configurable Logic and Dedicated Logic Functions
App 20070085565 - Verma; Hare K. ;   et al.
2007-04-19
Programmable Logic Cells with Local Connections
App 20070085564 - Verma; Hare K. ;   et al.
2007-04-19
Dedicated Logic Cells Employing Sequential Logic and Contol Logic Functions
App 20070080711 - Verma; Hare K. ;   et al.
2007-04-12
Dedicated Logic Cells Employing Configurable Logic and Dedicated Logic Functions
App 20070075740 - Verma; Hare K. ;   et al.
2007-04-05
Dedicated Logic Cells Employing Sequential Logic and Control Logic Functions
App 20070075741 - Verma; Hare K. ;   et al.
2007-04-05
Dedicated Logic Cells Employing Configurable Logic and Dedicated Logic Functions
App 20070075739 - Verma; Hare K. ;   et al.
2007-04-05
High speed configurable transceiver architecture
Grant 7,187,709 - Menon , et al. March 6, 2
2007-03-06
Programmable logic and routing blocks with dedicated lines
Grant 7,176,717 - Sunkavalli , et al. February 13, 2
2007-02-13
Network physical layer with embedded multi-standard CRC generator
Grant 7,111,220 - Sasaki , et al. September 19, 2
2006-09-19
Dedicated logic cells employing configurable logic and dedicated logic functions
App 20060186919 - Verma; Hare K. ;   et al.
2006-08-24
Dedicated logic cells employing sequential logic and control logic functions
App 20060186918 - Verma; Hare K. ;   et al.
2006-08-24
Programmable logic cells with Local Connections
App 20060164120 - Verma; Hare K. ;   et al.
2006-07-27
Programmable logic and routing blocks with dedicated lines
App 20060158219 - Sunkavalli; Ravi ;   et al.
2006-07-20
Programmable integrated circuit architecture
Grant 6,980,029 - Vittal , et al. December 27, 2
2005-12-27
Variable data width operation in multi-gigabit transceivers on a programmable logic device
Grant 6,960,933 - Cory , et al. November 1, 2
2005-11-01
Low jitter clock for a physical media access sublayer on a field programmable gate array
Grant 6,911,842 - Ghia , et al. June 28, 2
2005-06-28
System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs
Grant 6,711,600 - Verma , et al. March 23, 2
2004-03-23
Variable data width operation in multi-gigabit transceivers on a programmable logic device
Grant 6,617,877 - Cory , et al. September 9, 2
2003-09-09
System and method for RAM-partitioning to exploit parallelism of RADIX-2 elements in FPGAs
Grant 6,317,768 - Verma , et al. November 13, 2
2001-11-13
Method for parallel-efficient configuring an FPGA for large FFTS and other vector rotation computations
Grant 6,021,423 - Nag , et al. February 1, 2
2000-02-01

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