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Patent applications and USPTO patent grants for Verita; Massimo.The latest application filed is for "temperature controlled structured asic manufactured on a 28 nm cmos process lithographic node".
Patent | Date |
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Digitally Controlled Delay Line for a Structured ASIC Having a Via Configurable Fabric for High-Speed Interface App 20140103985 - Andreev; Alexander ;   et al. | 2014-04-17 |
Temperature Controlled Structured ASIC Manufactured on a 28 NM CMOS Process Lithographic Node App 20140105246 - Andreev; Alexander ;   et al. | 2014-04-17 |
Microcontroller controlled or direct mode controlled network-fabric on a structured ASIC Grant 8,677,306 - Andreev , et al. March 18, 2 | 2014-03-18 |
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