Venugopal; Vivekanandan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Venugopal; Vivekanandan.The latest application filed is for "flip-flop circuit with glitch protection".
- Venugopal; Vivekanandan - San Jose CA
| Patent | Date |
|---|---|
| Low voltage clock swing tolerant sequential circuits for dynamic power savings Grant 11,424,734 - Venugopal , et al. August 23, 2 | 2022-08-23 |
| Efficient retention flop utilizing different voltage domain Grant 11,418,174 - Hess , et al. August 16, 2 | 2022-08-16 |
| Hybrid pulse/two-stage data latch Grant 11,418,173 - Venugopal , et al. August 16, 2 | 2022-08-16 |
| Flip-Flop Circuit with Glitch Protection App 20220231673 - Ye; Qi ; et al. | 2022-07-21 |
| Low power single retention pin flip-flop with balloon latch Grant 11,336,272 - Venugopal , et al. May 17, 2 | 2022-05-17 |
| Semi dynamic flop and single stage pulse flop with shadow latch and transparency on both input data edges Grant 11,303,268 - Venugopal , et al. April 12, 2 | 2022-04-12 |
| Low Power Single Retention Pin Flip-Flop with Balloon Latch App 20220094340 - Venugopal; Vivekanandan ; et al. | 2022-03-24 |
| No-enable setup clock gater based on pulse Grant 11,258,446 - Venugopal , et al. February 22, 2 | 2022-02-22 |
| Power Down Detection for Non-Destructive Isolation Signal Generation App 20220043469 - Venugopal; Vivekanandan ; et al. | 2022-02-10 |
| Low Voltage Clock Swing Tolerant Sequential Circuits for Dynamic Power Savings App 20210344329 - Venugopal; Vivekanandan ; et al. | 2021-11-04 |
| No-enable Setup Clock Gater Based On Pulse App 20210344344 - Venugopal; Vivekanandan ; et al. | 2021-11-04 |
| Level-shifting transparent window sense amplifier Grant 11,164,611 - Venugopal , et al. November 2, 2 | 2021-11-02 |
| Low power flip-flop with balanced clock-to-Q delay Grant 11,139,803 - Venugopal , et al. October 5, 2 | 2021-10-05 |
| Power down detection for non-destructive isolation signal generation Grant 11,132,010 - Venugopal , et al. September 28, 2 | 2021-09-28 |
| Efficient Retention Flop Utilizing Different Voltage Domain App 20210250019 - Hess; Greg M. ; et al. | 2021-08-12 |
| Semi Dynamic Flop and Single Stage Pulse Flop with Shadow Latch and Transparency on Both Input Data Edges App 20210167759 - Venugopal; Vivekanandan ; et al. | 2021-06-03 |
| Low voltage clock swing tolerant sequential circuits for dynamic power savings Grant 11,018,653 - Venugopal , et al. May 25, 2 | 2021-05-25 |
| Efficient retention flop utilizing different voltage domain Grant 11,005,459 - Hess , et al. May 11, 2 | 2021-05-11 |
| Pulsed level shifter circuitry Grant 10,903,824 - Venugopal , et al. January 26, 2 | 2021-01-26 |
| Hybrid Pulse/Two-Stage Data Latch App 20200373915 - Venugopal; Vivekanandan ; et al. | 2020-11-26 |
| Level shifter with isolation on both input and output domains with enable from both domains Grant 10,838,483 - Venugopal , et al. November 17, 2 | 2020-11-17 |
| Pulsed Level Shifter Circuitry App 20200313660 - Venugopal; Vivekanandan ; et al. | 2020-10-01 |
| Hybrid pulse/master-slave data latch Grant 10,742,201 - Venugopal , et al. A | 2020-08-11 |
| Level-shifting transparent window sense amplifier Grant 10,734,040 - Venugopal , et al. | 2020-08-04 |
| Hybrid power switch Grant 10,732,693 - Venugopal , et al. | 2020-08-04 |
| Level Shifter With Isolation On Both Input And Output Domains With Enable From Both Domains App 20200103957 - Venugopal; Vivekanandan ; et al. | 2020-04-02 |
| Hybrid Pulse/master-slave Data Latch App 20200106425 - Venugopal; Vivekanandan ; et al. | 2020-04-02 |
| Semi Dynamic Flop And Single Stage Pulse Flop With Shadow Latch And Transparency On Both Input Data Edges App 20200106424 - Venugopal; Vivekanandan ; et al. | 2020-04-02 |
| Pulsed level shifter circuitry Grant 10,581,412 - Venugopal , et al. | 2020-03-03 |
| Flop circuit with integrated clock gating circuit Grant 10,491,197 - Venugopal , et al. Nov | 2019-11-26 |
| Low power clock gating circuit Grant 10,461,747 - Venugopal , et al. Oc | 2019-10-29 |
| Hybrid Power Switch App 20190235602 - Venugopal; Vivekanandan ; et al. | 2019-08-01 |
| Master-slave clock generation circuit Grant 10,270,433 - Venugopal | 2019-04-23 |
| Hybrid power switch Grant 10,261,563 - Venugopal , et al. | 2019-04-16 |
| Low Power Clock Gating Circuit App 20190089354 - Venugopal; Vivekanandan ; et al. | 2019-03-21 |
| Flop Circuit with Integrated Clock Gating Circuit App 20190089337 - Venugopal; Vivekanandan ; et al. | 2019-03-21 |
| Level shifting circuit with data resolution and grounded input nodes Grant 10,187,061 - Venugopal , et al. Ja | 2019-01-22 |
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