Venkatraman; Ramnath

Patent Applications and Registrations

Patent applications and USPTO patent grants for Venkatraman; Ramnath.The latest application filed is for "closed-loop adaptive voltage scaling for integrated circuits".

Company Profile

0.36.28

Venkatraman; Ramnath - San Jose CA
Venkatraman; Ramnath - City of San Jose CA
Venkatraman; Ramnath - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Closed-loop Adaptive Voltage Scaling For Integrated Circuits App 20150109052 - Gowda; Manjunatha ; et al.	2015-04-23
Power controller for SoC power gating applications Grant 8,738,940 - Venkatraman , et al. May 27, 2	2014-05-27
Total Power Optimization For A Logic Integrated Circuit App 20140040842 - Mbouombouo; Benjamin ; et al.	2014-02-06
Critical Path Monitor Hardware Architecture For Closed Loop Adaptive Voltage Scaling And Method Of Operation Thereof App 20140028364 - Venkatraman; Ramnath ; et al.	2014-01-30
Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank Grant 8,624,352 - Weir , et al. January 7, 2	2014-01-07
Total power optimization for a logic integrated circuit Grant 8,589,853 - Mbouombouo , et al. November 19, 2	2013-11-19
Reducing Power Consumption Of Memory App 20130166930 - Zhou; Ting ; et al.	2013-06-27
Reducing Power Consumption Of Memory App 20130166931 - Castagnetti; Ruggero ; et al.	2013-06-27
Method Of Lowering Capacitances Of Conductive Apertures And An Interposer Capable Of Being Reverse Biased To Achieve Reduced Capacitance App 20130154109 - Venkatraman; Ramnath ; et al.	2013-06-20
Basic cell architecture for structured ASICs Grant 8,429,586 - Venkatraman , et al. April 23, 2	2013-04-23
Defectivity-immune technique of implementing MIM-based decoupling capacitors Grant 8,411,399 - Venkatraman , et al. April 2, 2	2013-04-02
Power Controller For Soc Power Gating Applications App 20130057338 - Venkatraman; Ramnath ; et al.	2013-03-07
Total Power Optimization For A Logic Integrated Circuit App 20120290994 - Mbouombouo; Benjamin ; et al.	2012-11-15
Basic Cell Architecture For Structured ASICs App 20120175683 - Venkatraman; Ramnath ; et al.	2012-07-12
Mitigation Of Detrimental Breakdown Of A High Dielectric Constant Metal-insulator-metal Capacitor In A Capacitor Bank App 20120126364 - Weir; Bonnie E. ; et al.	2012-05-24
Integrated circuit cell architecture configurable for memory or logic elements Grant 8,178,909 - Venkatraman , et al. May 15, 2	2012-05-15
Basic cell architecture for structured application-specific integrated circuits Grant 8,166,440 - Venkatraman , et al. April 24, 2	2012-04-24
Optimization with adaptive body biasing Grant 8,112,734 - Mbouombouo , et al. February 7, 2	2012-02-07
Integrated Circuit Cell Architecture Configurable for Memory or Logic Elements App 20120012896 - Venkatraman; Ramnath ; et al.	2012-01-19
Integrated circuit cell architecture configurable for memory or logic elements Grant 8,044,437 - Venkatraman , et al. October 25, 2	2011-10-25
Defectivity-immune Technique Of Implementing Mim-based Decoupling Capacitors App 20110051304 - Venkatraman; Ramnath ; et al.	2011-03-03
SRAM based one-time-programmable memory Grant 7,869,251 - Venkatraman , et al. January 11, 2	2011-01-11
Design Optimization With Adaptive Body Biasing App 20100083193 - Mbouombouo; Benjamin ; et al.	2010-04-01
Sram Based One-time-programmable Memory App 20100080035 - Venkatraman; Ramnath ; et al.	2010-04-01
Modular design of multiport memory bitcells Grant 7,440,356 - Venkatraman , et al. October 21, 2	2008-10-21
Basic cell architecture for structured application-specific integrated circuits Grant 7,404,154 - Venkatraman , et al. July 22, 2	2008-07-22
Modular design of multiport memory bitcells App 20080013383 - Venkatraman; Ramnath ; et al.	2008-01-17
Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas Grant 7,304,874 - Venkatraman , et al. December 4, 2	2007-12-04
Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas App 20060203530 - Venkatraman; Ramnath ; et al.	2006-09-14
Circuit for verifying the write speed of SRAM cells Grant 7,082,067 - Venkatraman , et al. July 25, 2	2006-07-25
Optical proximity correction method using weighted priorities Grant 7,069,535 - Kobozeva , et al. June 27, 2	2006-06-27
Ternary CAM bitcells Grant 7,042,747 - Castagnetti , et al. May 9, 2	2006-05-09
Circuit for verifying the write speed of SRAM cells App 20060050600 - Venkatraman; Ramnath ; et al.	2006-03-09
Design and use of a spacer cell to support reconfigurable memories Grant 7,006,369 - Venkatraman , et al. February 28, 2	2006-02-28
Memory cell architecture Grant 7,006,370 - Ramesh , et al. February 28, 2	2006-02-28
Memory cell architecture for reduced routing congestion Grant 6,980,462 - Ramesh , et al. December 27, 2	2005-12-27
Reconfigurable memory arrays Grant 6,934,174 - Castagnetti , et al. August 23, 2	2005-08-23
Reconfigurable memory arrays App 20050047238 - Castagnetti, Ruggero ; et al.	2005-03-03
Design and use of a spacer cell to support reconfigurable memories App 20050047254 - Venkatraman, Ramnath ; et al.	2005-03-03
Optical proximity correction method using weighted priorities App 20040250232 - Kobozeva, Olga A. ; et al.	2004-12-09
Method of forming metal fuses in CMOS processes with copper interconnect Grant 6,828,653 - Castagnetti , et al. December 7, 2	2004-12-07
Fuse construction for integrated circuit structure having low dielectric constant dielectric material Grant 6,806,551 - Liu , et al. October 19, 2	2004-10-19
Method of forming semiconductor device including interconnect barrier layers Grant 6,713,381 - Barr , et al. March 30, 2	2004-03-30
Method of forming metal fuses in CMOS processes with copper interconnect Grant 6,664,141 - Castagnetti , et al. December 16, 2	2003-12-16
Fuse construction for integrated circuit structure having low dielectric constant dielectric material App 20030164532 - Liu, Yauh-Ching ; et al.	2003-09-04
Semiconductor device and method of formation App 20020093098 - Barr, Alexander L. ; et al.	2002-07-18
Semiconductor Device Conductive Bump And Interconnect Barrier App 20020000665 - BARR, ALEXANDER L. ; et al.	2002-01-03
Method for forming a semiconductor device Grant 6,218,302 - Braeckelmann , et al. April 17, 2	2001-04-17
Copper interconnect structure and method of formation Grant 6,174,810 - Islam , et al. January 16, 2	2001-01-16
Semiconductor device with a copper barrier layer and formation thereof Grant 6,093,966 - Venkatraman , et al. July 25, 2	2000-07-25
Process for fabricating a multilevel interconnect Grant 6,077,768 - Ong , et al. June 20, 2	2000-06-20
Method of forming an interconnect structure Grant 5,814,557 - Venkatraman , et al. September 29, 1	1998-09-29
Process for fabricating a metallized interconnect Grant 5,783,485 - Ong , et al. July 21, 1	1998-07-21
Method of alloying an interconnect structure with copper Grant 5,677,244 - Venkatraman October 14, 1	1997-10-14