| Patent | Date |
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Semiconductor device with transistor local interconnects
Grant 11,444,031 - Rashed , et al. September 13, 2 | 2022-09-13 |
Optical dielectric waveguide subassembly structures
Grant 11,422,306 - Venkatesan , et al. August 23, 2 | 2022-08-23 |
Optical Dielectric Planar Waveguide Process
App 20220043210 - Ring; William ; et al. | 2022-02-10 |
Method Of Forming An Hermetic Seal On Electronic And Optoelectronic Packages
App 20210389532 - Lam; Yee Loy ; et al. | 2021-12-16 |
Loopback Waveguide
App 20210356517 - Venkatesan; Suresh ; et al. | 2021-11-18 |
Structure And Method For Testing Of Pic With An Upturned Mirror
App 20210356518 - Soldano; Lucas ; et al. | 2021-11-18 |
Structure And Method For Testing Of Pic With An Upturned Mirror
App 20210356519 - Soldano; Lucas ; et al. | 2021-11-18 |
Loopback Waveguide
App 20210333473 - Venkatesan; Suresh ; et al. | 2021-10-28 |
Optical dielectric planar waveguide process
Grant 11,156,779 - Ring , et al. October 26, 2 | 2021-10-26 |
Method of forming an hermetic seal on electronic and optoelectronic packages
Grant 11,099,338 - Lam , et al. August 24, 2 | 2021-08-24 |
Dual Core Waveguide
App 20210255396 - Venkatesan; Suresh ; et al. | 2021-08-19 |
Dual Core Waveguide
App 20210231877 - Venkatesan; Suresh ; et al. | 2021-07-29 |
Methods for Optical Dielectric Waveguide Structures
App 20210215876 - Ring; William ; et al. | 2021-07-15 |
Planar Laser Structure with Vertical Signal Transition
App 20210126429 - Venkatesan; Suresh | 2021-04-29 |
Dual core waveguide
Grant 10,976,497 - Venkatesan , et al. April 13, 2 | 2021-04-13 |
Dual core waveguide
Grant 10,976,496 - Venkatesan , et al. April 13, 2 | 2021-04-13 |
Methods for optical dielectric waveguide structures
Grant 10,962,715 - Ring , et al. March 30, 2 | 2021-03-30 |
Methods For Optical Dielectric Waveguide Structure
App 20210080649 - Venkatesan; Suresh ; et al. | 2021-03-18 |
Semiconductor Device With Transistor Local Interconnects
App 20210013150 - Rashed; Mahbub ; et al. | 2021-01-14 |
Semiconductor device with transistor local interconnects
Grant 10,833,018 - Rashed , et al. November 10, 2 | 2020-11-10 |
Optical Dielectric Planar Waveguide Process
App 20200348468 - Ring; William ; et al. | 2020-11-05 |
Methods for optical dielectric waveguide subassembly structure
Grant 10,795,079 - Venkatesan , et al. October 6, 2 | 2020-10-06 |
Optical Dielectric Waveguide Subassembly Structures
App 20200278495 - Venkatesan; Suresh ; et al. | 2020-09-03 |
Dual Core Waveguide
App 20200257053 - A1 | 2020-08-13 |
Dual Core Waveguide
App 20200257054 - A1 | 2020-08-13 |
Optical dielectric planar waveguide process
Grant 10,718,905 - Ring , et al. | 2020-07-21 |
Optical dielectric waveguide subassembly structures
Grant 10,663,660 - Venkatesan , et al. | 2020-05-26 |
Vertical cavity surface emitting laser
Grant 10,530,125 - Venkatesan J | 2020-01-07 |
Method Of Forming An Hermetic Seal On Electronic And Optoelectronic Packages
App 20190361180 - Lam; Yee Loy ; et al. | 2019-11-28 |
Semiconductor Device With Transistor Local Interconnects
App 20190326219 - Rashed; Mahbub ; et al. | 2019-10-24 |
Optical Dielectric Planar Waveguide Process
App 20190271810 - Ring; William ; et al. | 2019-09-05 |
Optical Dielectric Waveguide Subassembly Structures
App 20190243078 - Venkatesan; Suresh ; et al. | 2019-08-08 |
Methods for Optical Dielectric Waveguide Structures
App 20190227234 - Ring; Bill ; et al. | 2019-07-25 |
Methods For Optical Dielectric Waveguide Subassembly Structure
App 20190227232 - Venkatesan; Suresh ; et al. | 2019-07-25 |
Automation Testing Platform For Facilitating Automatic Testing Of An Information Technology (it) Enabled Application
App 20180322035 - MOHANTY; Avishek ; et al. | 2018-11-08 |
Semiconductor Device With Transistor Local Interconnects
App 20160268204 - Rashed; Mahbub ; et al. | 2016-09-15 |
Semiconductor device with transistor local interconnects
Grant 9,355,910 - Rashed , et al. May 31, 2 | 2016-05-31 |
Methods of using a trench salicide routing layer
Grant 9,196,548 - Rashed , et al. November 24, 2 | 2015-11-24 |
Forming Gate Tie Between Abutting Cells And Resulting Device
App 20150311122 - RASHED; Mahbub ; et al. | 2015-10-29 |
Middle-of-the-line constructs using diffusion contact structures
Grant 9,142,513 - Rashed , et al. September 22, 2 | 2015-09-22 |
Middle-of-the-line Constructs Using Diffusion Contact Structures
App 20150187702 - RASHED; Mahbub ; et al. | 2015-07-02 |
Densely Packed Standard Cells For Integrated Circuit Products, And Methods Of Making Same
App 20150108583 - Rashed; Mahbub ; et al. | 2015-04-23 |
Middle-of-the-line constructs using diffusion contact structures
Grant 9,006,100 - Rashed , et al. April 14, 2 | 2015-04-14 |
Cross-coupling based design using diffusion contact structures
Grant 8,987,128 - Rashed , et al. March 24, 2 | 2015-03-24 |
Densely packed standard cells for integrated circuit products, and methods of making same
Grant 8,975,712 - Rashed , et al. March 10, 2 | 2015-03-10 |
FinFET device and methods of fabrication
Grant 8,916,441 - Rashed , et al. December 23, 2 | 2014-12-23 |
Densely Packed Standard Cells For Integrated Circuit Products, And Methods Of Making Same
App 20140339647 - Rashed; Mahbub ; et al. | 2014-11-20 |
Finfet Device And Method Of Fabrication
App 20140339610 - Rashed; Mahbub ; et al. | 2014-11-20 |
Variable power rail design
Grant 8,789,000 - Rashed , et al. July 22, 2 | 2014-07-22 |
Methods Of Using A Trench Salicide Routing Layer
App 20140183638 - RASHED; Mahbub ; et al. | 2014-07-03 |
Providing timing-closed FinFET designs from planar designs
Grant 8,689,154 - Rashed , et al. April 1, 2 | 2014-04-01 |
Middle-of-the-line Constructs Using Diffusion Contact Structures
App 20140042641 - Rashed; Mahbub ; et al. | 2014-02-13 |
Cross-coupling Based Design Using Diffusion Contact Structures
App 20140027918 - Rashed; Mahbub ; et al. | 2014-01-30 |
Semiconductor Devices Formed On A Continuous Active Region With An Isolating Conductive Structure Positioned Between Such Semiconductor Devices, And Methods Of Making Same
App 20140001563 - Rashed; Mahbub ; et al. | 2014-01-02 |
Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same
Grant 8,618,607 - Rashed , et al. December 31, 2 | 2013-12-31 |
Intelligent work load manager
Grant 8,621,074 - Shikari , et al. December 31, 2 | 2013-12-31 |
Semiconductor device having contact layer providing electrical connections
Grant 8,598,633 - Tarabbia , et al. December 3, 2 | 2013-12-03 |
Semiconductor device with transistor local interconnects
Grant 8,581,348 - Rashed , et al. November 12, 2 | 2013-11-12 |
Intelligent Work Load Manager
App 20130290513 - Shikari; Faiyaz ; et al. | 2013-10-31 |
Providing Timing-closed Finfet Designs From Planar Designs
App 20130275935 - Rashed; Mahbub ; et al. | 2013-10-17 |
Semiconductor Device
App 20130181289 - Tarabbia; Marc ; et al. | 2013-07-18 |
Semiconductor Device With Transistor Local Interconnects
App 20130146986 - Rashed; Mahbub ; et al. | 2013-06-13 |
Semiconductor Device With Transistor Local Interconnects
App 20130146982 - Rashed; Mahbub ; et al. | 2013-06-13 |
Mos Semiconductor Device And Methods For Its Fabrication
App 20120267724 - VENKATESAN; Suresh | 2012-10-25 |
Separate layer formation in a semiconductor device
Grant 8,039,339 - Grant , et al. October 18, 2 | 2011-10-18 |
Method and apparatus for mobility enhancement in a semiconductor device
Grant 7,872,311 - Orlowski , et al. January 18, 2 | 2011-01-18 |
Method of forming a semiconductor isolation trench
Grant 7,687,370 - Van Gompel , et al. March 30, 2 | 2010-03-30 |
Deep STI trench and SOI undercut enabling STI oxide stressor
Grant 7,678,665 - Turner , et al. March 16, 2 | 2010-03-16 |
Process for forming an electronic device including semiconductor fins
Grant 7,456,055 - Orlowski , et al. November 25, 2 | 2008-11-25 |
Separate Layer Formation In A Semiconductor Device
App 20080261374 - Grant; John M. ; et al. | 2008-10-23 |
Deep STI trench and SOI undercut enabling STI oxide stressor
App 20080220617 - Turner; Michael D. ; et al. | 2008-09-11 |
Method And Apparatus For Mobility Enhancement In A Semiconductor Device
App 20080006880 - Orlowski; Marius K. ; et al. | 2008-01-10 |
Method and apparatus for mobility enhancement in a semiconductor device
Grant 7,288,448 - Orlowski , et al. October 30, 2 | 2007-10-30 |
Electronic device including a semiconductor fin and a process for forming the electronic device
App 20070218628 - Orlowski; Marius K. ; et al. | 2007-09-20 |
Method of forming a semiconductor isolation trench
App 20070178661 - Gompel; Toni D. Van ; et al. | 2007-08-02 |
Semiconductor Device With Multiple Semiconductor Layers
App 20060194384 - Venkatesan; Suresh ; et al. | 2006-08-31 |
Memory with recessed devices
Grant 7,078,297 - Burnett , et al. July 18, 2 | 2006-07-18 |
Method and apparatus for mobility enhancement in a semiconductor device
App 20060046366 - Orlowski; Marius K. ; et al. | 2006-03-02 |
Semiconductor device with multiple semiconductor layers
App 20050275018 - Venkatesan, Suresh ; et al. | 2005-12-15 |
Memory with recessed devices
App 20050266643 - Burnett, James D. ; et al. | 2005-12-01 |
Method of forming semiconductor device including interconnect barrier layers
Grant 6,713,381 - Barr , et al. March 30, 2 | 2004-03-30 |
Hetero-integration of semiconductor materials on silicon
App 20040012037 - Venkatesan, Suresh ; et al. | 2004-01-22 |
Method for forming a dual inlaid copper interconnect structure
Grant 6,551,919 - Venkatesan , et al. April 22, 2 | 2003-04-22 |
Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process
App 20020151167 - Farkas, Janos ; et al. | 2002-10-17 |
Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process
Grant 6,444,569 - Farkas , et al. September 3, 2 | 2002-09-03 |
Semiconductor device and method of formation
App 20020093098 - Barr, Alexander L. ; et al. | 2002-07-18 |
Method for forming a dual inlaid copper interconnect structure
App 20020039836 - Venkatesan, Suresh ; et al. | 2002-04-04 |
Method for forming a semiconductor device
Grant 6,362,057 - Taylor, Jr. , et al. March 26, 2 | 2002-03-26 |
Semiconductor Device Conductive Bump And Interconnect Barrier
App 20020000665 - BARR, ALEXANDER L. ; et al. | 2002-01-03 |
Method for forming a dual inlaid copper interconnect structure
Grant 6,326,301 - Venkatesan , et al. December 4, 2 | 2001-12-04 |
Method for forming a copper interconnect using a multi-platen chemical mechanical polishing (CMP) process
App 20010027083 - Farkas, Janos ; et al. | 2001-10-04 |
Method for forming an MOS transistor having a metallic gate electrode that is formed after the formation of self-aligned source and drain regions
Grant 5,960,270 - Misra , et al. September 28, 1 | 1999-09-28 |
Process for fabricating a fully self-aligned soi mosfet
Grant 5,736,435 - Venkatesan , et al. April 7, 1 | 1998-04-07 |
Method for making CMOS device having reduced parasitic capacitance
Grant 5,627,097 - Venkatesan , et al. May 6, 1 | 1997-05-06 |
Integrated circuit having both vertical and horizontal devices and process for making the same
Grant 5,554,870 - Fitch , et al. September 10, 1 | 1996-09-10 |
Process for fabricating a semiconductor device using dual planarization layers
Grant 5,459,096 - Venkatesan , et al. October 17, 1 | 1995-10-17 |
Dual-gated semiconductor-on-insulator field effect transistor
Grant 5,349,228 - Neudeck , et al. September 20, 1 | 1994-09-20 |
Methods for fabricating a dual-gated semiconductor-on-insulator field effect transistor
Grant 5,273,921 - Neudeck , et al. December 28, 1 | 1993-12-28 |
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