Veeraraghavan; Sathish

Patent Applications and Registrations

Patent applications and USPTO patent grants for Veeraraghavan; Sathish.The latest application filed is for "process-induced distortion prediction and feedforward and feedback correction of overlay errors".

Company Profile

5.16.15

Veeraraghavan; Sathish - Santa Clara CA

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Patent Activity

Patent	Date
Breakdown analysis of geometry induced overlay and utilization of breakdown analysis for improved overlay control Grant 10,509,329 - Veeraraghavan , et al. Dec	2019-12-17
Process-Induced Distortion Prediction and Feedforward and Feedback Correction of Overlay Errors App 20190353582 - Vukkadala; Pradeep ; et al.	2019-11-21
Systems, Methods And Metrics For Wafer High Order Shape Characterization And Wafer Classification Using Wafer Dimensional Geomet App 20190271654 - Chen; Haiguang ; et al.	2019-09-05
Process-induced distortion prediction and feedforward and feedback correction of overlay errors Grant 10,401,279 - Vukkadala , et al. Sep	2019-09-03
Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool Grant 10,379,061 - Chen , et al. A	2019-08-13
Overlay and semiconductor process control using a wafer geometry metric Grant 10,249,523 - Vukkadala , et al.	2019-04-02
System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking Grant 10,025,894 - Vukkadala , et al. July 17, 2	2018-07-17
Systems and methods for effective pattern wafer surface measurement and analysis using interferometry tool Grant 9,865,047 - Chen , et al. January 9, 2	2018-01-09
Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry Grant 9,558,545 - Vukkadala , et al. January 31, 2	2017-01-31
Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool Grant 9,546,862 - Chen , et al. January 17, 2	2017-01-17
Overlay and Semiconductor Process Control Using a Wafer Geometry Metric App 20160372353 - Vukkadala; Pradeep ; et al.	2016-12-22
Using wafer geometry to improve scanner correction effectiveness for overlay control Grant 9,513,565 - MacNaughton , et al. December 6, 2	2016-12-06
System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking App 20160283625 - Vukkadala; Pradeep ; et al.	2016-09-29
System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking Grant 9,430,593 - Vukkadala , et al. August 30, 2	2016-08-30
Predicting and Controlling Critical Dimension Issues and Pattern Defectivity in Wafers Using Interferometry App 20160163033 - Vukkadala; Pradeep ; et al.	2016-06-09
Overlay and semiconductor process control using a wafer geometry metric Grant 9,354,526 - Vukkadala , et al. May 31, 2	2016-05-31
Breakdown Analysis of Geometry Induced Overlay and Utilization of Breakdown Analysis for Improved Overlay Control App 20160062252 - Veeraraghavan; Sathish ; et al.	2016-03-03
Using Wafer Geometry to Improve Scanner Correction Effectiveness for Overlay Control App 20150212429 - MacNaughton; Craig ; et al.	2015-07-30
Using wafer geometry to improve scanner correction effectiveness for overlay control Grant 9,029,810 - MacNaughton , et al. May 12, 2	2015-05-12
Process-Induced Distortion Prediction and Feedforward and Feedback Correction of Overlay Errors App 20150120216 - Vukkadala; Pradeep ; et al.	2015-04-30
Using Wafer Geometry to Improve Scanner Correction Effectiveness for Overlay Control App 20140353527 - MacNaughton; Craig ; et al.	2014-12-04
Site based quantification of substrate topography and its relation to lithography defocus and overlay Grant 8,768,665 - Veeraraghavan , et al. July 1, 2	2014-07-01
Systems, Methods and Metrics for Wafer High Order Shape Characterization and Wafer Classification Using Wafer Dimensional Geometry Tool App 20140114597 - Chen; Haiguang ; et al.	2014-04-24
System and Method to Emulate Finite Element Model Based Prediction of In-Plane Distortions Due to Semiconductor Wafer Chucking App 20140107998 - Vukkadala; Pradeep ; et al.	2014-04-17
Overlay And Semiconductor Process Control Using A Wafer Geometry Metric App 20130089935 - Vukkadala; Pradeep ; et al.	2013-04-11
Localized substrate geometry characterization Grant 8,065,109 - Veeraraghavan , et al. November 22, 2	2011-11-22
Site Based Quantification Of Substrate Topography And Its Relation To Lithography Defocus And Overlay App 20110172982 - Veeraraghavan; Sathish ; et al.	2011-07-14
Localized Substrate Geometry Characterization App 20110144943 - Veeraraghavan; Sathish ; et al.	2011-06-16

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