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name:-0.0074689388275146
name:-0.028677940368652
name:-0.0012390613555908
Vasudev, Prahalad K. Patent Filings

Vasudev, Prahalad K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vasudev, Prahalad K..The latest application filed is for "block downconverter using a sbar bandpass filter in a superheterodyne receiver".

Company Profile
0.22.2
  • Vasudev, Prahalad K. - Austin TX
  • Vasudev; Prahalad K. - Thousand Oaks CA
  • Vasudev; Prahalad K. - Santa Monica CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Block downconverter using a SBAR bandpass filter in a superheterodyne receiver
App 20020111151 - Irion, Reed A. ;   et al.
2002-08-15
State variable filter including a programmable variable resistor
App 20010033196 - Lennous, Paul A. ;   et al.
2001-10-25
Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
Grant 6,100,184 - Zhao , et al. August 8, 2
2000-08-08
Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
Grant 6,037,664 - Zhao , et al. March 14, 2
2000-03-14
Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications
Grant 5,891,513 - Dubin , et al. April 6, 1
1999-04-06
Electroless deposition equipment or apparatus and method of performing electroless deposition
Grant 5,830,805 - Shacham-Diamand , et al. November 3, 1
1998-11-03
Protected encapsulation of catalytic layer for electroless copper interconnect
Grant 5,824,599 - Schacham-Diamand , et al. October 20, 1
1998-10-20
Use of cobalt tungsten phosphide as a barrier material for copper metallization
Grant 5,695,810 - Dubin , et al. December 9, 1
1997-12-09
Selective electroless copper deposited interconnect plugs for ULSI applications
Grant 5,674,787 - Zhao , et al. October 7, 1
1997-10-07
Attenuated phase shifting mask with buried absorbers
Grant 5,480,747 - Vasudev January 2, 1
1996-01-02
Globally planarized binary optical mask using buried absorbers
Grant 5,474,865 - Vasudev December 12, 1
1995-12-12
Method of fabricating phase shifters with absorbing/attenuating sidewalls using an additive process
Grant 5,418,095 - Vasudev , et al. May 23, 1
1995-05-23
Phase shifting mask structure with absorbing/attenuating sidewalls for improved imaging
Grant 5,411,824 - Vasudev , et al. May 2, 1
1995-05-02
Ultrathin submicron MOSFET with intrinsic channel
Grant 5,289,027 - Terrill , et al. February 22, 1
1994-02-22
Floating base lateral bipolar phototransistor with field effect gate voltage control
Grant 5,027,177 - Vasudev June 25, 1
1991-06-25
Silicon-on-sapphire liquid crystal light valve and method
Grant 4,826,300 - Efron , et al. May 2, 1
1989-05-02
Low leakage CMOS/insulator substrate devices and method of forming the same
Grant 4,816,893 - Mayer , et al. March 28, 1
1989-03-28
Method of forming low leakage CMOS device on insulating substrate
Grant 4,753,895 - Mayer , et al. June 28, 1
1988-06-28
Opposed dual-gate hybrid structure for three-dimensional integrated circuits
Grant 4,748,485 - Vasudev May 31, 1
1988-05-31
Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits
Grant 4,659,392 - Vasudev April 21, 1
1987-04-21
Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
Grant 4,617,066 - Vasudev October 14, 1
1986-10-14
Solid phase epitaxy and regrowth process with controlled defect density profiling for heteroepitaxial semiconductor on insulator composite substrates
Grant 4,509,990 - Vasudev April 9, 1
1985-04-09
Process for fabrication of monolithic transistor coupled electroluminescent diode
Grant 4,439,910 - Vasudev April 3, 1
1984-04-03
Monolithic transistor coupled electroluminescent diode
Grant 4,388,633 - Vasudev June 14, 1
1983-06-14

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