Vashi; Mehul R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vashi; Mehul R..The latest application filed is for "programmable gate array and embedded circuitry initialization and processing".

Company Profile

0.14.1

Vashi; Mehul R. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of and circuit for enabling variable latency data transfers Grant 7,624,209 - Ansari , et al. November 24, 2	2009-11-24
Programmable gate array and embedded circuitry initialization and processing Grant 7,420,392 - Schultz , et al. September 2, 2	2008-09-02
Method of enabling timing verification of a circuit design Grant 7,418,679 - Vashi , et al. August 26, 2	2008-08-26
Testing of an integrated circuit having an embedded processor Grant 7,406,670 - Ansari , et al. July 29, 2	2008-07-29
Circuit for and method of accessing instruction data written to a memory Grant 7,401,258 - Fang , et al. July 15, 2	2008-07-15
Method of and circuit for verifying a data transfer protocol Grant 7,333,909 - Vashi , et al. February 19, 2	2008-02-19
Testing of an integrated circuit having an embedded processor Grant 7,269,805 - Ansari , et al. September 11, 2	2007-09-11
Method of and circuit for verifying a data transfer protocol Grant 7,139,673 - Vashi , et al. November 21, 2	2006-11-21
Generation of design views having consistent input/output pin definitions Grant 7,117,471 - Li , et al. October 3, 2	2006-10-03
Method and apparatus for synchronized buses Grant 7,007,121 - Ansari , et al. February 28, 2	2006-02-28
Method and system for controlling default values of flip-flops in PGA/ASIC-based designs Grant 6,976,160 - Yin , et al. December 13, 2	2005-12-13
Programmable gate array and embedded circuitry initialization and processing App 20050040850 - Schultz, David P. ; et al.	2005-02-24
Programmable gate array having interconnecting logic to support embedded fixed logic circuitry Grant 6,798,239 - Douglass , et al. September 28, 2	2004-09-28
User configurable memory system having local and global memory blocks Grant 6,662,285 - Douglass , et al. December 9, 2	2003-12-09
User configurable on-chip memory system Grant 6,522,167 - Ansari , et al. February 18, 2	2003-02-18

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.