Varshney; Ramesh C.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Varshney; Ramesh C..The latest application filed is for "wafer level integration technique".
- Varshney; Ramesh C. - San Jose CA
| Patent | Date |
|---|---|
| Wafer level integration technique Grant 4,703,436 - Varshney October 27, 1 | 1987-10-27 |
| Low power clock generator Grant 4,496,852 - Blaser , et al. January 29, 1 | 1985-01-29 |
| Test system for segmented memory Grant 4,495,603 - Varshney January 22, 1 | 1985-01-22 |
| Serial-parallel-serial charged coupled device memory and a method of transferring charge therein Grant 4,493,060 - Varshney January 8, 1 | 1985-01-08 |
| Identification of repaired integrated circuits Grant 4,480,199 - Varshney , et al. October 30, 1 | 1984-10-30 |
| Method and means for internal error check in a digital memory Grant 4,384,353 - Varshney May 17, 1 | 1983-05-17 |
| Method of forming recessed isolation oxide layers Grant 4,272,308 - Varshney June 9, 1 | 1981-06-09 |
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