loadpatents
name:-0.011162042617798
name:-0.020151853561401
name:-0.0007178783416748
Variot; Patrick Patent Filings

Variot; Patrick

Patent Applications and Registrations

Patent applications and USPTO patent grants for Variot; Patrick.The latest application filed is for "region shielding within a package of a microelectronic device".

Company Profile
0.18.7
  • Variot; Patrick - Los Gatos CA
  • Variot; Patrick - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Region Shielding Within A Package Of A Microelectronic Device
App 20220139846 - Variot; Patrick ;   et al.
2022-05-05
3d-Interconnect
App 20210366857 - Chia; Chok J. ;   et al.
2021-11-25
3D-interconnect
Grant 11,031,362 - Chia , et al. June 8, 2
2021-06-08
3D-Interconnect
App 20190148324 - Chia; Chok J. ;   et al.
2019-05-16
3D-interconnect
Grant 10,181,447 - Chia , et al. Ja
2019-01-15
3d-interconnect
App 20180308813 - Chia; Chok J. ;   et al.
2018-10-25
Electronic device package and method of manufacture
Grant 8,384,205 - Low , et al. February 26, 2
2013-02-26
Flip-chip Package And Method Of Manufacturing The Same Using Ablation
App 20120018901 - Variot; Patrick ;   et al.
2012-01-26
Electronic Device Package And Method Of Manufacture
App 20110260324 - Low; Qwai ;   et al.
2011-10-27
Electronic device package and method of manufacture
Grant 7,993,981 - Low , et al. August 9, 2
2011-08-09
Electronic Device Package And Method Of Manufacture
App 20100314747 - Low; Qwai ;   et al.
2010-12-16
Bondable anodized aluminum heatspreader for semiconductor packages
Grant 6,297,550 - Chia , et al. October 2, 2
2001-10-02
Method for planarizing an array of solder balls
Grant 6,088,914 - Variot , et al. July 18, 2
2000-07-18
Method for compensating for bottom warpage of a BGA integrated circuit
Grant 5,989,937 - Variot , et al. November 23, 1
1999-11-23
Process for using a removeable plating bus layer for high density substrates
Grant 5,981,311 - Chia , et al. November 9, 1
1999-11-09
Method of providing electrical connection between an integrated circuit die and a printed circuit board
Grant 5,933,710 - Chia , et al. August 3, 1
1999-08-03
Ball grid array package employing solid core solder balls
Grant 5,841,198 - Chia , et al. November 24, 1
1998-11-24
Method of planarizing an array of plastically deformable contacts on an integrated circuit package to compensate for surface warpage
Grant 5,745,986 - Variot , et al. May 5, 1
1998-05-05
Method for encapsulating an integrated circuit package
Grant 5,692,296 - Variot December 2, 1
1997-12-02
Apparatus for encapsulating an integrated circuit package
Grant 5,570,272 - Variot October 29, 1
1996-10-29
Surface mount peripheral leaded and ball grid array package
Grant 5,563,446 - Chia , et al. October 8, 1
1996-10-08
Overmolded semiconductor package
Grant 5,557,150 - Variot , et al. September 17, 1
1996-09-17
Integrated circuit having a coplanar solder ball contact array
Grant 5,435,482 - Variot , et al. July 25, 1
1995-07-25
GPT system for encapsulating an integrated circuit package
Grant 5,420,752 - Variot May 30, 1
1995-05-30

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