Varghese; Ajith

Patent Applications and Registrations

Patent applications and USPTO patent grants for Varghese; Ajith.The latest application filed is for "transistor performance using a two-step damage anneal".

Company Profile

0.16.22

Varghese; Ajith - McKinney TX
Varghese; Ajith - Austin TX
Varghese; Ajith - McKinnery TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Transistor performance using a two-step damage anneal Grant 9,054,056 - Niimi , et al. June 9, 2	2015-06-09
Transistor performance using a two-step damage anneal Grant 9,029,251 - Niimi , et al. May 12, 2	2015-05-12
Transistor Performance Using A Two-step Damage Anneal App 20140339609 - Niimi; Hiroaki ; et al.	2014-11-20
Transistor Performance Using A Two-step Damage Anneal App 20140342521 - Niimi; Hiroaki ; et al.	2014-11-20
Transistor performance using a two-step damage anneal Grant 8,828,855 - Niimi , et al. September 9, 2	2014-09-09
Mitigation of gate to contact capacitance in CMOS flow Grant 8,119,470 - Ekbote , et al. February 21, 2	2012-02-21
Border region defect reduction in hybrid orientation technology (HOT) direct silicon bonded (DSB) substrates Grant 7,855,111 - Bu , et al. December 21, 2	2010-12-21
Highly selective liners for semiconductor fabrication Grant 7,838,370 - Mehta , et al. November 23, 2	2010-11-23
Low temperature polysilicon oxide process for high-K dielectric/metal gate stack Grant 7,723,173 - Varghese , et al. May 25, 2	2010-05-25
Semiconductor device manufactured using a non-contact implant metrology Grant 7,696,021 - Mehta , et al. April 13, 2	2010-04-13
Thermal treatment of nitrided oxide to improve negative bias thermal instability Grant 7,682,988 - Alshareef , et al. March 23, 2	2010-03-23
Border Region Defect Reduction In Hybrid Orientation Technology (hot) Direct Silicon Bonded (dsb) Substrates App 20100032727 - Bu; Haowen ; et al.	2010-02-11
Low Temperature Polysilicon Oxide Process For High-k Dielectric/metal Gate Stack App 20090170346 - Varghese; Ajith ; et al.	2009-07-02
CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers Grant 7,514,308 - Varghese , et al. April 7, 2	2009-04-07
Methodology for Reducing Post Burn-In Vmin Drift App 20090045472 - Chakravarthi; Srinivasan ; et al.	2009-02-19
Method To Obtain Uniform Nitrogen Profile In Gate Dielectrics App 20080315324 - VARGHESE; AJITH ; et al.	2008-12-25
Transistor Performance Using A Two-step Damage Anneal App 20080268627 - Niimi; Hiroaki ; et al.	2008-10-30
Transistor Performance Using A Two-step Damage Anneal App 20080268603 - NIIMI; Hiroaki ; et al.	2008-10-30
Stacked Poly Structure To Reduce The Poly Particle Count In Advanced Cmos Technology App 20080251864 - Chen; Yuanning ; et al.	2008-10-16
Method to obtain uniform nitrogen profile in gate dielectrics Grant 7,435,651 - Varghese , et al. October 14, 2	2008-10-14
Low Temperature Poly Oxide Processes For High-k/metal Gate Flow App 20080246099 - Varghese; Ajith ; et al.	2008-10-09
Mitigation of gate to contact capacitance in CMOS flow App 20080230815 - Ekbote; Shashank Sureshchandra ; et al.	2008-09-25
Highly Selective Liners For Semiconductor Fabrication App 20080217703 - Mehta; Narendra Singh ; et al.	2008-09-11
Methods of improving drive currents by employing strain inducing STI liners Grant 7,396,728 - Varghese , et al. July 8, 2	2008-07-08
Strain modulation employing process techniques for CMOS technologies Grant 7,384,861 - Mehta , et al. June 10, 2	2008-06-10
Rework Methodology That Preserves Gate Performance App 20080076076 - Obeng; Yaw Samuel ; et al.	2008-03-27
Semiconductor Device Manufactured Using a Non-Contact Implant Metrology App 20080006886 - Mehta; Narendra Singh ; et al.	2008-01-10
CMOS Device Having Different Amounts of Nitrogen in the NMOS Gate Dielectric Layers and PMOS Gate Dielectric Layers App 20070207572 - Varghese; Ajith ; et al.	2007-09-06
CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers Grant 7,227,201 - Varghese , et al. June 5, 2	2007-06-05
Method to obtain uniform nitrogen profile in gate dielectrics App 20070054455 - Varghese; Ajith ; et al.	2007-03-08
Strain modulation employing process techniques for CMOS technologies App 20070015347 - Mehta; Narendra Singh ; et al.	2007-01-18
Methods of improving drive currents by employing strain inducing STI liners App 20070004118 - Varghese; Ajith ; et al.	2007-01-04
CMOS device having different amounts of nitrogen in the NMOS gate dielectric layers and PMOS gate dielectric layers App 20060043369 - Varghese; Ajith ; et al.	2006-03-02
Thermal treatment of nitrided oxide to improve negative bias thermal instability App 20060046514 - Alshareef; Husam N. ; et al.	2006-03-02
Method for removal of hydrocarbon contamination on gate oxide prior to non-thermal nitridation using "spike" radical oxidation Grant 6,924,239 - Niimi , et al. August 2, 2	2005-08-02
Method For Removal Of Hydrocarbon Contamination On Gate Oxide Prior To Non-thermal Nitridation Using "spike" Radical Oxidation App 20050079723 - Niimi, Hiroaki ; et al.	2005-04-14
Nitridation process for independent control of device gate leakage and drive current App 20040262701 - Alshareef, Husam N. ; et al.	2004-12-30

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