loadpatents
name:-0.0030219554901123
name:-0.012408018112183
name:-0.0015249252319336
Varadarajan; Ravi Patent Filings

Varadarajan; Ravi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Varadarajan; Ravi.The latest application filed is for "method of global design closure at top level and driving of downstream implementation flow".

Company Profile
0.10.2
  • Varadarajan; Ravi - Fremont CA
  • Varadarajan; Ravi - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method Of Global Design Closure At Top Level And Driving Of Downstream Implementation Flow
App 20140298281 - Varadarajan; Ravi ;   et al.
2014-10-02
Method of global design closure at top level and driving of downstream implementation flow
Grant 8,839,171 - Varadarajan , et al. September 16, 2
2014-09-16
Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysis
Grant 8,782,582 - Gupta , et al. July 15, 2
2014-07-15
Method for creating physical connections in 3D integrated circuits
Grant 8,732,647 - Rusu , et al. May 20, 2
2014-05-20
Bus representation for efficient physical synthesis of integrated circuit designs
Grant 7,451,427 - Varadarajan November 11, 2
2008-11-11
Bus Representation For Efficient Physical Synthesis Of Integrated Circuit Designs
App 20060282800 - Varadarajan; Ravi
2006-12-14
Optimized placement and routing of datapaths
Grant 5,838,583 - Varadarajan , et al. November 17, 1
1998-11-17
Virtual interface representation of hierarchical symbolic layouts
Grant 5,604,680 - Bamji , et al. February 18, 1
1997-02-18
Identifying overconstraints using port abstraction graphs
Grant 5,581,474 - Bamji , et al. December 3, 1
1996-12-03
Identifying overconstraints using port abstraction graphs
Grant 5,568,396 - Bamji , et al. October 22, 1
1996-10-22
Hier archical pitchmaking compaction method and system for integrated circuit design
Grant 5,381,343 - Bamji , et al. January 10, 1
1995-01-10
Cloning method and system for hierarchical compaction
Grant 5,281,558 - Bamji , et al. January 25, 1
1994-01-25

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