loadpatents
name:-0.016571998596191
name:-0.017665863037109
name:-0.0051889419555664
Vang; Foua Patent Filings

Vang; Foua

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vang; Foua.The latest application filed is for "heterogeneous height logic cell architecture".

Company Profile
5.16.18
  • Vang; Foua - Sacramento CA
  • Vang; Foua - Anaheim CA
  • Vang; Foua - Lemon Grove CA
  • VANG; Foua - San Diego CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits
Grant 11,437,379 - Song , et al. September 6, 2
2022-09-06
Circuits employing a back side-front side connection structure for coupling back side routing to front side routing, and related complementary metal oxide semiconductor (CMOS) circuits and methods
Grant 11,404,374 - Lim , et al. August 2, 2
2022-08-02
Heterogeneous Height Logic Cell Architecture
App 20220115405 - LIM; Hyeokjin ;   et al.
2022-04-14
Circuits Employing A Back Side-front Side Connection Structure For Coupling Back Side Routing To Front Side Routing, And Related Complementary Metal Oxide Semiconductor (cmos) Circuits And Methods
App 20220102266 - Lim; Hyeokjin ;   et al.
2022-03-31
Multibit multi-height cell to improve pin accessibility
Grant 11,290,109 - Vang , et al. March 29, 2
2022-03-29
Multibit Multi-height Cell To Improve Pin Accessibility
App 20220094363 - VANG; Foua ;   et al.
2022-03-24
Field-effect Transistors (fet) Circuits Employing Topside And Backside Contacts For Topside And Backside Routing Of Fet Power And Logic Signals, And Related Complementary Metal Oxide Semiconductor (cmos) Circuits
App 20220093594 - SONG; Stanley Seungchul ;   et al.
2022-03-24
Systems and methods providing leakage reduction for power gated domains
Grant 11,237,580 - Samson , et al. February 1, 2
2022-02-01
Vertical Power Grid Standard Cell Architecture
App 20210280571 - LIM; Hyeokjin ;   et al.
2021-09-09
High performance cell design in a technology with high density metal routing
Grant 10,692,808 - Hiremath , et al.
2020-06-23
Standard cell architecture with M1 layer unidirectional routing
Grant 10,593,700 - Gupta , et al.
2020-03-17
High Performance Cell Design In A Technology With High Density Metal Routing
App 20190088591 - Hiremath; Renukprasad ;   et al.
2019-03-21
Hybrid coloring methodology for multi-pattern technology
Grant 10,175,571 - Chen , et al. J
2019-01-08
Standard Cell Architecture With M1 Layer Unidirectional Routing
App 20180122824 - GUPTA; Mukul ;   et al.
2018-05-03
Standard cell architecture with M1 layer unidirectional routing
Grant 9,887,209 - Gupta , et al. February 6, 2
2018-02-06
Hybrid Coloring Methodology For Multi-pattern Technology
App 20160370699 - CHEN; Xiangdong ;   et al.
2016-12-22
Grounding dummy gate in scaled layout design
Grant 9,379,058 - Song , et al. June 28, 2
2016-06-28
High performance standard cell with continuous oxide definition and characterized leakage current
Grant 9,318,476 - Chen , et al. April 19, 2
2016-04-19
Standard Cell Architecture With M1 Layer Unidirectional Routing
App 20150333008 - GUPTA; Mukul ;   et al.
2015-11-19
Mask Assignment Technique For M1 Metal Layer In Triple-patterning Lithography
App 20150302129 - CHEN; Xiangdong ;   et al.
2015-10-22
High Performance Standard Cell
App 20150249076 - CHEN; XIANGDONG ;   et al.
2015-09-03
Grounding Dummy Gate In Scaled Layout Design
App 20150235948 - SONG; Stanley Seungchul ;   et al.
2015-08-20
Decoupling capacitor for integrated circuit
Grant 9,053,960 - Kamal , et al. June 9, 2
2015-06-09
Shared-diffusion standard cell architecture
Grant 8,836,040 - Kamal , et al. September 16, 2
2014-09-16
Decoupling Capacitor For Integrated Circuit
App 20140246715 - Kamal; Pratyush ;   et al.
2014-09-04
Shared-diffusion Standard Cell Architecture
App 20140124868 - Kamal; Pratyush ;   et al.
2014-05-08
Standard cell architecture using double poly patterning for multi VT devices
Grant 8,610,176 - Patel , et al. December 17, 2
2013-12-17
Techniques providing fiducial markers for failure analysis
Grant 8,420,410 - Laisne , et al. April 16, 2
2013-04-16
Area Efficient Gridded Polysilicon Layouts
App 20130032885 - Swamynathan; Chethan ;   et al.
2013-02-07
Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices
App 20120180016 - Chidambaram; PR ;   et al.
2012-07-12
Techniques Providing Fiducial Markers For Failure Analysis
App 20110164808 - Laisne; Michael ;   et al.
2011-07-07

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