Van Meer; Johannes

Patent Applications and Registrations

Patent applications and USPTO patent grants for Van Meer; Johannes.The latest application filed is for "fin damage reduction during punch through implantation of finfet device".

Company Profile

13.16.10

Van Meer; Johannes - Middleton MA
van Meer; Johannes - Newburgh NY US
van Meer; Johannes - Fishkill NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Replacement gate formation with angled etch and deposition Grant 11,217,491 - Sung , et al. January 4, 2	2022-01-04
Structure and method of forming fin device having improved fin liner Grant 10,971,403 - Sung , et al. April 6, 2	2021-04-06
Method of forming transistor device having fin cut regions Grant 10,720,357 - Sung , et al.	2020-07-21
Fin damage reduction during punch through implantation of FinFET device Grant 10,692,775 - Sung , et al.	2020-06-23
Fin damage reduction during punch through implantation of FinFET device Grant 10,686,033 - Sung , et al.	2020-06-16
Method and device for power rail in a fin type field effect transistor Grant 10,685,865 - Sung , et al.	2020-06-16
Fin Damage Reduction During Punch Through Implantation Of Finfet Device App 20200152519 - Sung; Min Gyu ; et al.	2020-05-14
Fin Damage Reduction During Punch Through Implantation Of Finfet Device App 20200152735 - Sung; Min Gyu ; et al.	2020-05-14
Structure And Method Of Forming Fin Device Having Improved Fin Liner App 20200135573 - Sung; Min Gyu ; et al.	2020-04-30
Method And Device For Shallow Trench Isolation In A Fin Type Field Effect Transistors App 20200135928 - Sung; Min Gyu ; et al.	2020-04-30
Method and device for shallow trench isolation in a fin type field effect transistors Grant 10,629,741 - Sung , et al.	2020-04-21
Techniques for forming device having etch-resistant isolation oxide Grant 10,510,870 - Sung , et al. Dec	2019-12-17
Structure and method of forming fin device having improved fin liner Grant 10,510,610 - Sung , et al. Dec	2019-12-17
Replacement Gate Formation With Angled Etch And Deposition App 20190341315 - Sung; Min Gyu ; et al.	2019-11-07
Structure And Method Of Forming Fin Device Having Improved Fin Liner App 20190304841 - Sung; Min Gyu ; et al.	2019-10-03
Method Of Forming Transistor Device Having Fin Cut Regions App 20190273011 - Sung; Min Gyu ; et al.	2019-09-05
Replacement gate formation with angled etch and deposition Grant 10,403,552 - Sung , et al. Sep	2019-09-03
Structure And Method Of Forming Device Having Improved Isolation Oxide App 20190259859 - Sung; Min Gyu ; et al.	2019-08-22
CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layer Grant 9,373,548 - Pei , et al. June 21, 2	2016-06-21
Methods of forming multiple N-type semiconductor devices with different threshold voltages on a semiconductor substrate Grant 8,846,476 - Liu , et al. September 30, 2	2014-09-30
Methods Of Forming Multiple N-type Semiconductor Devices With Different Threshold Voltages On A Semiconductor Substrate App 20140227845 - Liu; Yanxiang ; et al.	2014-08-14
Raised source and drain process with disposable spacers Grant 7,745,296 - van Meer , et al. June 29, 2	2010-06-29
Stress Enhanced Cmos Circuits App 20090008718 - PEI; Gen ; et al.	2009-01-08
Stress enhanced CMOS circuits and methods for their fabrication Grant 7,442,601 - Pei , et al. October 28, 2	2008-10-28
Method for fabricating a semiconductor device Grant 7,329,599 - Wirbeleit , et al. February 12, 2	2008-02-12

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.