van Laarhoven; Josephus M. F. G.
Patent Applications and Registrations
Patent applications and USPTO patent grants for van Laarhoven; Josephus M. F. G..The latest application filed is for "method of forming a configuration of interconnections on a semiconductor device having a high integration density".
- van Laarhoven; Josephus M. F. G. - Eindhoven NL
| Patent | Date |
|---|---|
| Method of forming a configuration of interconnections on a semiconductor device having a high integration density Grant RE34,583 - Grief , et al. April 12, 1 | 1994-04-12 |
| Selectively plating conductive pillars in manufacturing a semiconductor device Grant 5,063,169 - De Bruin , et al. November 5, 1 | 1991-11-05 |
| Method of manufacturing a semiconductor device by forming insulating side walls with voids below overhangs Grant 5,001,079 - van Laarhoven , et al. March 19, 1 | 1991-03-19 |
| Method of manufacturing a semiconductor device Grant 4,956,312 - Van Laarhoven September 11, 1 | 1990-09-11 |
| Method of enabling electrical connection to a substructure forming part of an electronic device Grant 4,948,459 - van Laarhoven , et al. August 14, 1 | 1990-08-14 |
| Forming electrical connections for electronic devices Grant 4,946,550 - Van Laarhoven August 7, 1 | 1990-08-07 |
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