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Vector processor system Grant 8,356,144 - Hessel , et al. January 15, 2 | 2013-01-15 |
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Detecting conditions for transfer of execution from one computer instruction stream to another and executing transfer on satisfaction of the conditions Grant 8,121,828 - Yates, Jr. , et al. February 21, 2 | 2012-02-21 |
Altering data storage conventions of a processor when execution flows from first architecture code to second architecture code Grant 8,074,055 - Yates, Jr. , et al. December 6, 2 | 2011-12-06 |
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Computer for executing two instruction sets and adds a macroinstruction end marker for performing iterations after loop termination Grant 7,941,647 - Yates, Jr. , et al. May 10, 2 | 2011-05-10 |
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Vector processor Grant 7,543,119 - Hessel , et al. June 2, 2 | 2009-06-02 |
Apparatus for executing programs for a first computer architechture on a computer of a second architechture App 20080216073 - Yates; John S. ;   et al. | 2008-09-04 |
Vector processor App 20070255894 - Hessel; Richard Edward ;   et al. | 2007-11-01 |
Detecting reordered side-effects Grant 7,254,806 - Yates, Jr. , et al. August 7, 2 | 2007-08-07 |
Managing instruction side-effects Grant 7,228,404 - Patel , et al. June 5, 2 | 2007-06-05 |
Side tables annotating an instruction stream Grant 7,069,421 - Yates, Jr. , et al. June 27, 2 | 2006-06-27 |
System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU Grant 7,065,633 - Yates, Jr. , et al. June 20, 2 | 2006-06-20 |
Computer for execution of RISC and CISC instruction sets Grant 7,047,394 - Van Dyke , et al. May 16, 2 | 2006-05-16 |
Profiling execution of computer programs Grant 7,013,456 - Van Dyke , et al. March 14, 2 | 2006-03-14 |
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Profiling of computer programs executing in virtual memory systems Grant 6,941,545 - Reese , et al. September 6, 2 | 2005-09-06 |
Exception mechanism for a computer Grant 6,934,832 - Van Dyke , et al. August 23, 2 | 2005-08-23 |
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Profiling program execution into registers of a computer Grant 6,826,748 - Hohensee , et al. November 30, 2 | 2004-11-30 |
Safety net paradigm for managing two computer execution modes Grant 6,789,181 - Yates , et al. September 7, 2 | 2004-09-07 |
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Variable length instruction alignment device and method Grant 6,654,872 - Ramesh , et al. November 25, 2 | 2003-11-25 |
Detecting modification to computer memory by a DMA device Grant 6,549,959 - Yates , et al. April 15, 2 | 2003-04-15 |
Method and apparatus for debugging an integrated circuit Grant 6,499,123 - McFarland , et al. December 24, 2 | 2002-12-24 |
Method and apparatus for busing data elements Grant 6,449,671 - Patkar , et al. September 10, 2 | 2002-09-10 |
Branch prediction device with two levels of branch prediction cache Grant 6,425,075 - Stiles , et al. July 23, 2 | 2002-07-23 |
Recording in a program execution profile references to a memory-mapped active device Grant 6,397,379 - Yates, Jr. , et al. May 28, 2 | 2002-05-28 |
Method and apparatus for restricting memory access Grant 6,321,314 - Van Dyke November 20, 2 | 2001-11-20 |
Method and apparatus for executing string instructions Grant 6,212,629 - McFarland , et al. April 3, 2 | 2001-04-03 |
Branch prediction device with two levels of branch prediction cache Grant 6,067,616 - Stiles , et al. May 23, 2 | 2000-05-23 |
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Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions Grant 5,768,575 - McFarland , et al. June 16, 1 | 1998-06-16 |
Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence Grant 5,748,932 - Van Dyke , et al. May 5, 1 | 1998-05-05 |
Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts Grant 5,682,492 - McFarland , et al. October 28, 1 | 1997-10-28 |
Processor having primary integer execution unit and supplemental integer execution unit for performing out-of-order add and move operations Grant 5,675,758 - Sowadsky , et al. October 7, 1 | 1997-10-07 |
Branch prediction cache with multiple entries for returns having multiple callers Grant 5,623,614 - Van Dyke , et al. April 22, 1 | 1997-04-22 |
Superscalar execution unit for sequential instruction pointer updates and segment limit checks Grant 5,590,351 - Sowadsky , et al. December 31, 1 | 1996-12-31 |
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Configurable branch prediction for a processor performing speculative execution Grant 5,454,117 - Puziol , et al. September 26, 1 | 1995-09-26 |
Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts Grant 5,442,757 - McFarland , et al. * August 15, 1 | 1995-08-15 |
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Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags Grant 5,226,126 - McFarland , et al. July 6, 1 | 1993-07-06 |
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