loadpatents
name:-0.0035879611968994
name:-0.026235103607178
name:-0.00044107437133789
Van Antwerpen; Babette Patent Filings

Van Antwerpen; Babette

Patent Applications and Registrations

Patent applications and USPTO patent grants for Van Antwerpen; Babette.The latest application filed is for "systems and methods for tracking synthesis optimizations for circuit designs".

Company Profile
0.25.2
  • Van Antwerpen; Babette - Mountain View CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Systems And Methods For Tracking Synthesis Optimizations For Circuit Designs
App 20220277123 - Van Antwerpen; Babette ;   et al.
2022-09-01
Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement
Grant 9,230,047 - Van Antwerpen , et al. January 5, 2
2016-01-05
Register retiming technique
Grant 9,053,274 - van Antwerpen , et al. June 9, 2
2015-06-09
Method and apparatus for performing parallel synthesis on a field programmable gate array
Grant 8,954,906 - Baeckler , et al. February 10, 2
2015-02-10
Register retiming technique
Grant 8,806,399 - van Antwerpen , et al. August 12, 2
2014-08-12
Method and apparatus for performing parallel synthesis on a field programmable gate array
Grant 8,661,380 - Baeckler , et al. February 25, 2
2014-02-25
Register retiming technique
Grant 8,402,408 - van Antwerpen , et al. March 19, 2
2013-03-19
Tracing and reporting registers removed during synthesis
Grant 8,166,427 - Pathak , et al. April 24, 2
2012-04-24
Register retiming technique
Grant 8,108,812 - van Antwerpen , et al. January 31, 2
2012-01-31
Recognizing muliplexers
Grant 7,945,877 - Van Antwerpen May 17, 2
2011-05-17
Register retiming technique
Grant 7,689,955 - van Antwerpen , et al. March 30, 2
2010-03-30
Methods and apparatus for error checking code decomposition
Grant 7,634,705 - Baeckler , et al. December 15, 2
2009-12-15
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
Grant 7,594,208 - Borer , et al. September 22, 2
2009-09-22
User-directed timing-driven synthesis
Grant 7,587,688 - Van Antwerpen , et al. September 8, 2
2009-09-08
State machine recognition and optimization
Grant 7,441,212 - van Antwerpen , et al. October 21, 2
2008-10-21
Local searching techniques for technology mapping
Grant 7,418,690 - Van Antwerpen August 26, 2
2008-08-26
Method and apparatus for reducing synthesis runtime
Grant 7,415,693 - van Antwerpen , et al. August 19, 2
2008-08-19
Physical resynthesis of a logic design
Grant 7,337,100 - Hutton , et al. February 26, 2
2008-02-26
Timing-driven synthesis with area trade-off
Grant 7,246,340 - Van Antwerpen , et al. July 17, 2
2007-07-17
Fast method for functional mapping to incomplete LUT pairs
Grant 7,224,183 - Baeckler , et al. May 29, 2
2007-05-29
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage
Grant 7,181,703 - Borer , et al. February 20, 2
2007-02-20
Fast method for functional mapping to incomplete LUT pairs
App 20070035327 - Baeckler; Gregg William ;   et al.
2007-02-15
Estimating quality during early synthesis
Grant 7,171,633 - Hwang , et al. January 30, 2
2007-01-30
Register retiming technique
Grant 7,120,883 - van Antwerpen , et al. October 10, 2
2006-10-10

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