Vajana; Bruno

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vajana; Bruno.The latest application filed is for "anti-deciphering contacts".

Company Profile

0.10.12

Vajana; Bruno - Bergamo IT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions Grant 6,624,015 - Patelmo , et al. September 23, 2	2003-09-23
Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication Grant 6,614,080 - Vajana , et al. September 2, 2	2003-09-02
Anti-deciphering contacts Grant 6,528,885 - Vajana , et al. March 4, 2	2003-03-04
Process for manufacturing electronic devices comprising high voltage MOS transistors, and electronic device thus obtained Grant 6,501,147 - Vajana , et al. December 31, 2	2002-12-31
Anti-deciphering contacts App 20020079564 - Vajana, Bruno ; et al.	2002-06-27
Mask programmed ROM inviolable by reverse engineering inspections and method of fabrication App 20020063268 - Vajana, Bruno ; et al.	2002-05-30
Low resistance contact structure for a select transistor of EEPROM memory cells in a NO-DPCC process App 20020060349 - Libera, Giovanna Dalla ; et al.	2002-05-23
Method for manufacturing electronic devices having non-volatile memory cells and LV transistors with salicided junctions App 20020040993 - Patelmo, Matteo ; et al.	2002-04-11
Memory cell of the EEPROM type having its threshold adjusted by implantation App 20020020872 - Cremonesi, Carlo ; et al.	2002-02-21
Process for producing a semiconductor memory device comprising mass-storage memory cells and shielded memory cells for storing reserved information App 20010025980 - Bottini, Roberta ; et al.	2001-10-04
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions App 20010024861 - Patelmo, Matteo ; et al.	2001-09-27
Integrated MOS transistor with a high threshold voltage and low multiplication coefficient App 20010022380 - Patelmo, Matteo ; et al.	2001-09-20
Process for the manufacturing of an electrically programmable non-volatile memory device App 20010021555 - Bottini, Roberta ; et al.	2001-09-13
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions App 20010021556 - Patelmo, Matteo ; et al.	2001-09-13
Method for manufacturing electronic devices comprising non-volatile memory cells and LV transistors with salicided junctions Grant 6,281,077 - Patelmo , et al. August 28, 2	2001-08-28
Method for manufacturing electronic devices, comprising non-salicided non-volatile memory cells, non-salicided HV transistors, and LV transistors with salicided junctions with few masks Grant 6,274,411 - Patelmo , et al. August 14, 2	2001-08-14
Method for manufacturing electronic devices having HV transistors and LV transistors with salicided junctions Grant 6,251,728 - Patelmo , et al. June 26, 2	2001-06-26
Method for forming a multilevel ROM memory in a dual gate CMOS process, and corresponding ROM memory cell App 20010001721 - Patelmo, Matteo ; et al.	2001-05-24
Nonvolatile Semiconductor Memory Device Structure With Superimposed Bit Lines And Short-circuit Metal Strips App 20010001492 - ZATELLI, NICOLA ; et al.	2001-05-24
EEPROM memory cell comprising a selection transistor with threshold voltage adjusted by implantation, and related manufacturing process Grant 6,221,717 - Cremonesi , et al. April 24, 2	2001-04-24
Bipolar transistor compatible with CMOS processes Grant 5,793,085 - Vajana , et al. August 11, 1	1998-08-11
Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells Grant 5,322,803 - Cappelletti , et al. June 21, 1	1994-06-21

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