Vaed; Kunal

Patent Applications and Registrations

Patent applications and USPTO patent grants for Vaed; Kunal.The latest application filed is for "methods of fabricating passive element without planarizing and related semiconductor device".

Company Profile

0.24.28

Vaed; Kunal - Poughkeepsie NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of fabricating passive element without planarizing and related semiconductor device Grant 8,487,401 - Chinthakindi , et al. July 16, 2	2013-07-16
Methods Of Fabricating Passive Element Without Planarizing And Related Semiconductor Device App 20120133022 - Chinthakindi; Anil K. ; et al.	2012-05-31
Methods of fabricating passive element without planarizing and related semiconductor device Grant 8,119,491 - Chinthakindi , et al. February 21, 2	2012-02-21
Method Of Fabricating A Precision Buried Resistor App 20110108919 - Chinthakindi; Anil K. ; et al.	2011-05-12
Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material Grant 7,915,134 - Chinthakindi , et al. March 29, 2	2011-03-29
Method of fabricating a precision buried resistor Grant 7,910,450 - Chinthakindi , et al. March 22, 2	2011-03-22
Post last wiring level inductor using patterned plate process Grant 7,763,954 - Chinthakindi , et al. July 27, 2	2010-07-27
Post last wiring level inductor using patterned plate process Grant 7,741,698 - Chinthakindi , et al. June 22, 2	2010-06-22
Post last wiring level inductor using patterned plate process Grant 7,732,295 - Chinthakindi , et al. June 8, 2	2010-06-08
Post last wiring level inductor using patterned plate process Grant 7,732,294 - Chinthakindi , et al. June 8, 2	2010-06-08
Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof Grant 7,691,717 - Chinthakindi , et al. April 6, 2	2010-04-06
Air gap under on-chip passive device Grant 7,662,722 - Stamper , et al. February 16, 2	2010-02-16
Semiconductor device structures with backside contacts for improved heat dissipation and reduced parasitic resistance Grant 7,622,357 - Vaed , et al. November 24, 2	2009-11-24
Suspended transmission line structures in back end of line processing Grant 7,608,909 - Chinthakindi , et al. October 27, 2	2009-10-27
Post last wiring level inductor using patterned plate process Grant 7,573,117 - Chinthakindi , et al. August 11, 2	2009-08-11
MOS varactor with segmented gate doping Grant 7,545,007 - Greer , et al. June 9, 2	2009-06-09
Method of Integration of a MIM Capacitor with a Lower Plate of Metal Gate Material Formed on an STI Region or a Silicide Region Formed in or on the Surface of a Doped Well with a High K Dielectric Material App 20090004809 - Chinthakindi; Anil Kumar ; et al.	2009-01-01
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080293210 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080293233 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080290458 - Chinthakindi; Anil Kumar ; et al.	2008-11-27
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080277759 - Chinthakindi; Anil Kumar ; et al.	2008-11-13
Post Last Wiring Level Inductor Using Patterned Plate Process App 20080272458 - Chinthakindi; Anil Kumar ; et al.	2008-11-06
Method and structure for integrating MIM capacitors within dual damascene processing techniques Grant 7,439,151 - Coolbaugh , et al. October 21, 2	2008-10-21
Methods of fabricating passive element without planarizing Grant 7,427,550 - Chinthakindi , et al. September 23, 2	2008-09-23
Methods Of Fabricating Passive Element Without Planarizing And Related Semiconductor Device App 20080224259 - Chinthakindi; Anil K. ; et al.	2008-09-18
Post last wiring level inductor using patterned plate process Grant 7,410,894 - Chinthakindi , et al. August 12, 2	2008-08-12
Method And Structure For Integrating Mim Capacitors Within Dual Damascene Processing Techniques App 20080185684 - Coolbaugh; Douglas D. ; et al.	2008-08-07
Air Gap Under On-chip Passive Device App 20080173976 - Stamper; Anthony K. ; et al.	2008-07-24
Integrated Circuit (ic) Chip With One Or More Vertical Plate Capacitors And Method Of Making The Capacitors App 20080173981 - Chinthakindi; Anil K. ; et al.	2008-07-24
Methods of fabricating passive element without planarizing and related semiconductor device Grant 7,394,145 - Chinthakindi , et al. July 1, 2	2008-07-01
Polysilicon Containing Resistor With Enhanced Sheet Resistance Precision And Method For Fabrication Thereof App 20080122574 - Chinthakindi; Anil K. ; et al.	2008-05-29
Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric Grant 7,361,950 - Chinthakindi , et al. April 22, 2	2008-04-22
Hi-K dielectric layer deposition methods Grant 7,354,872 - Coolbaugh , et al. April 8, 2	2008-04-08
Method And Structure For Integrating Mim Capacitors Within Dual Damascene Processing Techniques App 20080064163 - Coolbaugh; Douglas D. ; et al.	2008-03-13
Methods Of Fabricating Passive Element Without Planarizing And Related Semiconductor Device App 20080054393 - Chinthakindi; Anil K. ; et al.	2008-03-06
Methods Of Fabricating Passive Element Without Planarizing And Related Semiconductor Device App 20080003759 - Chinthakindi; Anil K. ; et al.	2008-01-03
Semiconductor Device Structures With Backside Contacts For Improved Heat Dissipation And Reduced Parasitic Resistance App 20070275533 - Vaed; Kunal ; et al.	2007-11-29
Method Of Fabricating A Precision Buried Resistor App 20070194390 - Chinthakindi; Anil K. ; et al.	2007-08-23
Single Or Dual Damascene Via Level Wirings And/or Devices, And Methods Of Fabricating Same App 20070152332 - Chinthakindi; Anil K. ; et al.	2007-07-05
Integration Of A Mim Capacitor Over A Metal Gate Or Silicide With High-k Dielectric Materials App 20070057343 - Chinthakindi; Anil Kumar ; et al.	2007-03-15
Mos Varactor With Segmented Gate Doping App 20070029587 - Greer; Heidi L. ; et al.	2007-02-08
Post Last Wiring Level Inductor Using Patterned Plate Process App 20070026659 - Chinthakindi; Anil Kumar ; et al.	2007-02-01
Hi-k Dielectric Layer Deposition Methods App 20060270247 - Coolbaugh; Douglas D. ; et al.	2006-11-30
Method For Forming Suspended Transmission Line Structures In Back End Of Line Processing App 20060197119 - Chinthakindi; Anil K. ; et al.	2006-09-07
Method of forming suspended transmission line structures in back end of line processing Grant 7,005,371 - Chinthakindi , et al. February 28, 2	2006-02-28
Damascene integration scheme for developing metal-insulator-metal capacitors Grant 6,992,344 - Coolbaugh , et al. January 31, 2	2006-01-31
Method For Forming Suspended Transmission Line Structures In Back End Of Line Processing App 20050245063 - Chinthakindi, Anil K. ; et al.	2005-11-03
Prevention of Ta2O5 mim cap shorting in the beol anneal cycles Grant 6,940,117 - Coolbaugh , et al. September 6, 2	2005-09-06
Vertically-stacked co-planar transmission line structure for IC design App 20050062137 - Singh, Raminderpal ; et al.	2005-03-24
Damascene integration scheme for developing metal-insulator-metal capacitors App 20040113235 - Coolbaugh, Douglas D. ; et al.	2004-06-17
PREVENTION OF Ta2O5 MIM CAP SHORTING IN THE BEOL ANNEAL CYCLES App 20040104420 - Coolbaugh, Douglas D. ; et al.	2004-06-03

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