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name:-0.0045790672302246
name:-0.0080928802490234
name:-0.0026309490203857
VADI; Vasisht M. Patent Filings

VADI; Vasisht M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for VADI; Vasisht M..The latest application filed is for "design applications of buried power rails".

Company Profile
2.9.4
  • VADI; Vasisht M. - San Diego CA
  • Vadi; Vasisht M. - San Jose CA US
  • Vadi; Vasisht M. - Mountain View CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Design Applications Of Buried Power Rails
App 20220068815 - VADI; Vasisht M.
2022-03-03
Applications of buried power rails
Grant 11,195,797 - Vadi December 7, 2
2021-12-07
Design Applications Of Buried Power Rails
App 20200373240 - VADI; Vasisht M.
2020-11-26
Area Efficient Flop For Usage In Sdb Based Libraries And Low Voltage Applications
App 20200106426 - VADI; Vasisht M.
2020-04-02
Digital signal processing block with preadder stage
Grant 8,543,635 - Simkins , et al. September 24, 2
2013-09-24
Determining timing paths within a circuit block of a programmable integrated circuit
Grant 8,117,577 - Vadi , et al. February 14, 2
2012-02-14
Digital Signal Processing Block With Preadder Stage
App 20100191786 - Simkins; James M. ;   et al.
2010-07-29
Data monitoring for single event upset in a programmable logic device
Grant 7,283,409 - Voogel , et al. October 16, 2
2007-10-16
High speed configurable transceiver architecture
Grant 7,187,709 - Menon , et al. March 6, 2
2007-03-06
Data monitoring for single event upset in a programmable logic device
Grant 7,109,746 - Voogel , et al. September 19, 2
2006-09-19
Glitchless dynamic multiplexer with synchronous and asynchronous controls
Grant 6,975,145 - Vadi , et al. December 13, 2
2005-12-13
Low jitter clock for a physical media access sublayer on a field programmable gate array
Grant 6,911,842 - Ghia , et al. June 28, 2
2005-06-28

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