Uzelac; Lawrence S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Uzelac; Lawrence S..The latest application filed is for "method and apparatus for minimizing leakage current in semiconductor logic".

Company Profile

0.6.4

Uzelac; Lawrence S. - Auburn CA
Uzelac; Lawrence S. - Aubura CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for minimizing leakage current in semiconductor logic Grant 7,406,609 - Uzelac , et al. July 29, 2	2008-07-29
Method and apparatus for minimizing leakage current in semiconductor logic App 20060005059 - Uzelac; Lawrence S. ; et al.	2006-01-05
Method and apparatus for reducing sub-threshold off current for a real time clock circuit during battery operation Grant 6,957,354 - Uzelac , et al. October 18, 2	2005-10-18
Circuit in which the time delay of an input clock signal is dependent only on its logic phase width and a ratio of capacitances Grant 6,834,355 - Uzelac December 21, 2	2004-12-21
Method and apparatus for reducing sub-threshold off current for a real time clock circuit during battery operation App 20040054940 - Uzelac, Lawrence S. ; et al.	2004-03-18
Temperature compensated output driver Grant 6,650,170 - Uzelac November 18, 2	2003-11-18
Power-up logic reference circuit and related method Grant 6,617,874 - Uzelac September 9, 2	2003-09-09
Method and apparatus for changing bias levels to reduce CMOS leakage of a real time clock when switching to a battery mode of operation Grant 6,611,918 - Uzelac August 26, 2	2003-08-26
Power-up logic reference circuit and related method App 20030122579 - Uzelac, Lawrence S.	2003-07-03
Clock phase generator App 20020112194 - Uzelac, Lawrence S.	2002-08-15

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