loadpatents
name:-0.042487144470215
name:-0.083549976348877
name:-0.0079419612884521
Uratani; Munehiro Patent Filings

Uratani; Munehiro

Patent Applications and Registrations

Patent applications and USPTO patent grants for Uratani; Munehiro.The latest application filed is for "bus driver and semiconductor integrated circuit".

Company Profile
0.8.4
  • Uratani; Munehiro - Yamatokoriyama JP
  • Uratani; Munehiro - Tsukuba JP
  • Uratani; Munehiro - Yamatokoriyama-shi JP
  • Uratani, Munehiro - Tsukuba-shi JP
  • Uratani; Munehiro - Kashihara JP
  • Uratani; Munehiro - Kashiwara JP
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Power consumption controlling apparatus for high frequency amplifier
Grant 7,529,528 - Uratani , et al. May 5, 2
2009-05-05
Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program
Grant 7,447,289 - Uratani , et al. November 4, 2
2008-11-04
Bus driver with well voltage control section
Grant 7,248,095 - Uratani , et al. July 24, 2
2007-07-24
Bus driver and semiconductor integrated circuit
App 20060055449 - Uratani; Munehiro ;   et al.
2006-03-16
Power consumption controlling apparatus for high frequency amplifier
App 20060046668 - Uratani; Munehiro ;   et al.
2006-03-02
Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program
App 20040190665 - Uratani, Munehiro ;   et al.
2004-09-30
Parameterized designing method of data driven information processor employing self-timed pipeline control
Grant 6,546,542 - Yumoto , et al. April 8, 2
2003-04-08
Parameterized designing method of data driven information processor employing self-timed pipeline control
App 20020023250 - Yumoto, Manabu ;   et al.
2002-02-21
Absolute difference accumulator circuit
Grant 5,610,850 - Uratani , et al. March 11, 1
1997-03-11
Memory cell circuit with single bit line latch
Grant 5,353,251 - Uratani , et al. October 4, 1
1994-10-04
CMOS gate array
Grant 4,783,692 - Uratani November 8, 1
1988-11-08
CMOS tree decoder with speed enhancement by adjustment of gate width
Grant 4,684,829 - Uratani August 4, 1
1987-08-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed