Uramoto; Shinichi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Uramoto; Shinichi.The latest application filed is for "motion vector detecting device capable of accomodating a plurality of predictive modes".

Company Profile

0.17.1

Uramoto; Shinichi - Hyogo JP
Uramoto; Shinichi - Itami JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Motion vector detecting device capable of accommodating a plurality of predictive modes Grant 6,674,798 - Ishihara , et al. January 6, 2	2004-01-06
Motion vector detecting device capable of accomodating a plurality of predictive modes App 20020009144 - Ishihara, Kazuya ; et al.	2002-01-24
Picture decoding and display unit including a memory having reduce storage capacity for storing pixel data Grant 6,320,909 - Takabatake , et al. November 20, 2	2001-11-20
Decode apparatus that can accommodate dynamic change in sample data attribute during decoding process Grant 6,243,032 - Uramoto , et al. June 5, 2	2001-06-05
Unit for detecting motion vector for motion compensation Grant 5,949,486 - Ishihara , et al. September 7, 1	1999-09-07
Image decompressing apparatus with efficient image data transfer Grant 5,850,483 - Takabatake , et al. December 15, 1	1998-12-15
Moving picture decoding circuit Grant 5,699,117 - Uramoto , et al. December 16, 1	1997-12-16
Apparatus and method for detecting an overflow when shifting N bits of data Grant 5,497,340 - Uramoto , et al. March 5, 1	1996-03-05
Phase clocked latch having both parallel and shunt connected switches for transmission gates Grant 5,463,340 - Takabatake , et al. October 31, 1	1995-10-31
Motion vector detecting device for compensating for movements in a motion picture Grant 5,400,087 - Uramoto , et al. March 21, 1	1995-03-21
Read only memory for storing multi-data Grant 5,394,355 - Uramoto , et al. February 28, 1	1995-02-28
Semiconductor integrated circuit device having a memory and an operational unit integrated therein Grant 5,379,257 - Matsumura , et al. January 3, 1	1995-01-03
Arithmetical unit including accumulating operation Grant 5,375,079 - Uramoto , et al. December 20, 1	1994-12-20
Semiconductor memory device usable as static type memory and read-only memory and operating method therefor Grant 5,365,475 - Matsumura , et al. November 15, 1	1994-11-15
Read only memory for storing multi-data Grant 5,289,406 - Uramoto , et al. February 22, 1	1994-02-22
DCT/IDCT processor and data processing method Grant 5,249,146 - Uramoto , et al. September 28, 1	1993-09-28
Output buffer circuit and method of operation thereof with reduced power consumption Grant 5,204,558 - Kumaki , et al. April 20, 1	1993-04-20
Output circuit for semiconductor integrated circuits having controllable load drive capability and operating method thereof Grant 5,185,538 - Kondoh , et al. February 9, 1	1993-02-09

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