| Patent | Date |
|---|
Method and apparatus for clearing hazards using jump instructions
Grant 8,171,262 - Jeppesen , et al. May 1, 2 | 2012-05-01 |
Method and apparatus for binding shadow registers to vectored interrupts
Grant 7,925,864 - Uhler April 12, 2 | 2011-04-12 |
Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions
Grant 7,853,777 - Jones , et al. December 14, 2 | 2010-12-14 |
Processor having a compare extension of an instruction set architecture
Grant 7,724,261 - Thekkath , et al. May 25, 2 | 2010-05-25 |
Configurable prioritization of core generated interrupts
Grant 7,552,261 - Uhler June 23, 2 | 2009-06-23 |
Method And Apparatus For Binding Shadow Registers To Vectored Interrupts
App 20090119434 - UHLER; G. Michael | 2009-05-07 |
Method and apparatus for binding shadow registers to vectored interrupts
Grant 7,487,339 - Uhler February 3, 2 | 2009-02-03 |
Processor having a compare extension of an instruction set architecture
App 20080022077 - Thekkath; Radhika ; et al. | 2008-01-24 |
Processor having a compare extension of an instruction set architecture
Grant 7,242,414 - Thekkath , et al. July 10, 2 | 2007-07-10 |
Method And Apparatus For Binding Shadow Registers To Vectored Interrupts
App 20070124569 - Uhler; G. Michael | 2007-05-31 |
Atomic update of CPO state
Grant 7,185,183 - Uhler February 27, 2 | 2007-02-27 |
Read-only access to CPO registers
Grant 7,181,600 - Uhler February 20, 2 | 2007-02-20 |
Method And Apparatus For Binding Shadow Registers To Vectored Interrupts
App 20060253635 - Uhler; G. Michael | 2006-11-09 |
Instruction/skid buffers in a multithreading microprocessor
App 20060179274 - Jones; Darren M. ; et al. | 2006-08-10 |
System and method for speeding up EJTAG block data transfers
Grant 7,065,675 - Thekkath , et al. June 20, 2 | 2006-06-20 |
Method and apparatus for clearing hazards using jump instructions
App 20060101255 - Jeppesen; Niels Gram ; et al. | 2006-05-11 |
Method and apparatus for clearing hazards using jump instructions
Grant 7,000,095 - Jeppesen , et al. February 14, 2 | 2006-02-14 |
Apparatus and method for preventing duplicate matching entries in a translation lookaside buffer
App 20050182903 - Kinter, Ryan C. ; et al. | 2005-08-18 |
Processor having a conditional branch extension of an instruction set architecture
Grant 6,732,259 - Thekkath , et al. May 4, 2 | 2004-05-04 |
Processor having an arithmetic extension of an instruction set architecture
Grant 6,714,197 - Thekkath , et al. March 30, 2 | 2004-03-30 |
Method and apparatus for clearing hazards using jump instructions
App 20040049660 - Jeppesen, Niels Gram ; et al. | 2004-03-11 |
Coherent data apparatus for an on-chip split transaction system bus
Grant 6,681,283 - Thekkath , et al. January 20, 2 | 2004-01-20 |
Mechanism for extending properties of virtual memory pages by a TLB
Grant 6,651,156 - Courtright , et al. November 18, 2 | 2003-11-18 |
Data release to reduce latency in on-chip system bus
Grant 6,604,159 - Thekkath , et al. August 5, 2 | 2003-08-05 |
Method and apparatus for binding shadow registers to vectored interrupts
App 20030074545 - Uhler, G. Michael | 2003-04-17 |
Configurable prioritization of core generated interrupts
App 20030074508 - Uhler, G. Michael | 2003-04-17 |
Scalable on-chip system bus
Grant 6,493,776 - Courtright , et al. December 10, 2 | 2002-12-10 |
Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory read
Grant 6,240,508 - Brown, III , et al. May 29, 2 | 2001-05-29 |
Method and apparatus for tracing unpredictable execution flows in a trace buffer of a high-speed computer system
Grant 5,802,272 - Sites , et al. September 1, 1 | 1998-09-01 |
Multi-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactions
Grant 5,579,504 - Callander , et al. November 26, 1 | 1996-11-26 |
Pipelined computer with operand context queue to simplify context-dependent execution flow
Grant 5,542,058 - Brown, III , et al. July 30, 1 | 1996-07-30 |
Conversion of internal processor register commands to I/O space addresses
Grant 5,481,689 - Stamm , et al. January 2, 1 | 1996-01-02 |
Computer system performance evaluation system and method
Grant 5,450,349 - Brown, III , et al. September 12, 1 | 1995-09-12 |
Application of state silos for recovery from memory management exceptions
Grant 5,119,483 - Madden , et al. June 2, 1 | 1992-06-02 |
Method and apparatus for filtering invalidate requests
Grant 5,058,006 - Durdan , et al. October 15, 1 | 1991-10-15 |
Central processor unit for digital data processing system including write buffer management mechanism
Grant 4,851,991 - Rubinfeld , et al. July 25, 1 | 1989-07-25 |
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