Tzou; Joseph

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tzou; Joseph.The latest application filed is for "access methods and circuits for memory devices having multiple banks".

Company Profile

0.23.6

Tzou; Joseph - Mountain View CA
Tzou; Joseph - Belmont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Access methods and circuits for memory devices having multiple banks Grant 9,666,255 - Tran , et al. May 30, 2	2017-05-30
Access methods and circuits for memory devices having multiple channels and multiple banks Grant 9,640,237 - Li , et al. May 2, 2	2017-05-02
Access Methods And Circuits For Memory Devices Having Multiple Banks App 20140340978 - Tran; Thinh ; et al.	2014-11-20
Data forwarding circuits and methods for memory devices with write latency Grant 8,873,264 - Tran , et al. October 28, 2	2014-10-28
Access methods and circuits for memory devices having multiple banks Grant 8,705,310 - Tran , et al. April 22, 2	2014-04-22
Access Methods And Circuits For Memory Devices Having Multiple Banks App 20140056093 - Tran; Thinh ; et al.	2014-02-27
Memory device data latency circuits and methods Grant 8,527,802 - Tran , et al. September 3, 2	2013-09-03
Memory device and method Grant 8,358,557 - Tzou , et al. January 22, 2	2013-01-22
Memory device and method Grant 8,149,643 - Tzou , et al. April 3, 2	2012-04-03
Memory Device And Method App 20120014202 - Tzou; Joseph ; et al.	2012-01-19
Memory system and method Grant 8,095,747 - Barbara , et al. January 10, 2	2012-01-10
Circuits and methods for programming integrated circuit input and output impedances Grant 8,040,164 - Parameswaran , et al. October 18, 2	2011-10-18
Memory having read disturb test mode Grant 7,719,908 - Tzou , et al. May 18, 2	2010-05-18
Memory device and method App 20100103762 - Tzou; Joseph ; et al.	2010-04-29
Memory System And Method App 20100082861 - Barbara; Bruce ; et al.	2010-04-01
Area efficient and fast static random access memory circuit and method Grant 7,684,257 - Lee , et al. March 23, 2	2010-03-23
Circuits and methods for programming integrated circuit input and output impedances App 20090085614 - Parameswaran; Suresh ; et al.	2009-04-02
Single late-write for standard synchronous SRAMs Grant 7,403,446 - Parameswaran , et al. July 22, 2	2008-07-22
Method and apparatus for built-in self-test (BIST) of integrated circuit device Grant 7,269,772 - Li , et al. September 11, 2	2007-09-11
Memory array with current limiting device for preventing particle induced latch-up Grant 7,196,925 - Tzou , et al. March 27, 2	2007-03-27
Hiding refresh in 1T-SRAM architecture Grant 7,146,454 - Li , et al. December 5, 2	2006-12-05
Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses Grant 7,142,477 - Tran , et al. November 28, 2	2006-11-28
Self-aligning contact and interconnect structure Grant 5,656,861 - Godinho , et al. August 12, 1	1997-08-12
Methods for fabricating integrated circuits including openings to transistor regions Grant 5,620,919 - Godinho , et al. April 15, 1	1997-04-15
Self-aligning contact and interconnect structure Grant 5,483,104 - Godinho , et al. * January 9, 1	1996-01-09
Method of fabricating a high resistance polysilicon load resistor Grant 5,168,076 - Godinho , et al. December 1, 1	1992-12-01
Self-aligning contact and interconnect structure Grant 5,166,771 - Godinho , et al. November 24, 1	1992-11-24
Compact SRAM cell layout Grant 5,124,774 - Godinho , et al. June 23, 1	1992-06-23

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