TZENG; Kuo-Chyuan

Patent Applications and Registrations

Patent applications and USPTO patent grants for TZENG; Kuo-Chyuan.The latest application filed is for "phase change memory device and method for manufacturing the same".

Company Profile

7.33.27

TZENG; Kuo-Chyuan - Hsinchu TW
Tzeng; Kuo-Chyuan - Chu-Pei TW
Tzeng; Kuo-Chyuan - Chu-Pei City TW
Tzeng; Kuo-Chyuan - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Phase Change Memory Device And Method For Manufacturing The Same App 20220293854 - TSENG; Yuan-Tai ; et al.	2022-09-15
Memory arrays including continuous line-shaped random access memory strips and method forming same Grant 11,404,480 - Lin , et al. August 2, 2	2022-08-02
Buffer Layer In Memory Cell To Prevent Metal Redeposition App 20220123207 - Min; Chung-Chiang ; et al.	2022-04-21
Bit Line And Word Line Connection For Memory Array App 20220115066 - Huang; Chang-Chih ; et al.	2022-04-14
Bit line and word line connection for memory array Grant 11,211,120 - Huang , et al. December 28, 2	2021-12-28
Bit Line And Word Line Connection For Memory Array App 20210295912 - Huang; Chang-Chih ; et al.	2021-09-23
Line-Shaped Memory and Method Forming Same App 20210202579 - Lin; Yi-Tzu ; et al.	2021-07-01
Self-aligned Double Patterning Process And Semiconductor Structure Formed Using Thereof App 20210035809 - Wang; Yu-Wen ; et al.	2021-02-04
Self-aligned double patterning (SADP) method Grant 10,872,777 - Pan , et al. December 22, 2	2020-12-22
Self-aligned double patterning process and semiconductor structure formed using thereof Grant 10,818,505 - Wang , et al. October 27, 2	2020-10-27
Self-aligned Double Patterning (sadp) Method App 20200098580 - Pan; Jui-Yu ; et al.	2020-03-26
Self-aligned Double Patterning Process And Semiconductor Structure Formed Using Thereof App 20200058514 - Wang; Yu-Wen ; et al.	2020-02-20
Self-aligned double patterning (SADP) method Grant 10,483,119 - Pan , et al. Nov	2019-11-19
Decoupling MIM capacitor designs for interposers and methods of manufacture thereof Grant 9,401,395 - Tzeng , et al. July 26, 2	2016-07-26
Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof App 20160155700 - Tzeng; Kuo-Chyuan ; et al.	2016-06-02
Metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers Grant 9,269,762 - Tzeng , et al. February 23, 2	2016-02-23
Decoupling MIM capacitor designs for interposers and methods of manufacture thereof Grant 9,263,415 - Tzeng , et al. February 16, 2	2016-02-16
Decoupling MIM capacitor designs for interposers and methods of manufacture thereof Grant 9,257,409 - Tzeng , et al. February 9, 2	2016-02-09
Metal-Insulator-Metal (MIM) Capacitor Within Topmost Thick Inter-Metal Dielectric Layers App 20150187866 - Tzeng; Kuo-Chyuan ; et al.	2015-07-02
Metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers Grant 8,994,146 - Tzeng , et al. March 31, 2	2015-03-31
Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers Grant 8,993,405 - Tzeng , et al. March 31, 2	2015-03-31
Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof App 20140235019 - Tzeng; Kuo-Chyuan ; et al.	2014-08-21
Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof App 20140217549 - Tzeng; Kuo-Chyuan ; et al.	2014-08-07
Method Of Fabricating Metal-insulator-metal (mim) Capacitor Within Topmost Thick Inter-metal Dielectric Layers App 20140191364 - Tzeng; Kuo-Chyuan ; et al.	2014-07-10
Method Of Fabricating Metal-insulator-metal (mim) Capacitor Within Topmost Thick Inter-metal Dielectric Layers App 20140193961 - Tzeng; Kuo-Chyuan ; et al.	2014-07-10
Method of manufacturing decoupling MIM capacitor designs for interposers Grant 8,748,284 - Tzeng , et al. June 10, 2	2014-06-10
Method of fabricating metal-insulator-metal (MIM) capacitor within topmost thick inter-metal dielectric layers Grant 8,716,100 - Tzeng , et al. May 6, 2	2014-05-06
Semiconductor devices with orientation-free decoupling capacitors and methods of manufacture thereof Grant 8,659,121 - Tu , et al. February 25, 2	2014-02-25
Metal-Insulator-Metal Capacitor and Method of Fabricating App 20130043560 - Tzeng; Kuo-Chyuan ; et al.	2013-02-21
Decoupling MIM Capacitor Designs for Interposers and Methods of Manufacture Thereof App 20130037910 - Tzeng; Kuo-Chyuan ; et al.	2013-02-14
Semiconductor Devices with Orientation-Free Decoupling Capacitors and Methods of Manufacture Thereof App 20130020678 - Tu; Kuo-Chi ; et al.	2013-01-24
Semiconductor devices and methods for fabricating the same Grant 8,012,836 - Tzeng , et al. September 6, 2	2011-09-06
One-transistor random access memory technology compatible with metal gate process Grant 7,884,408 - Tu , et al. February 8, 2	2011-02-08
Integrating a DRAM with an SRAM having butted contacts and resulting devices App 20080116496 - Tzeng; Kuo-Chyuan ; et al.	2008-05-22
Semiconductor devices and methods for fabricating the same App 20080079050 - Tzeng; Kuo-Chyuan ; et al.	2008-04-03
One-Transistor Random Access Memory Technology Compatible with Metal Gate Process App 20080073688 - Tu; Kuo-Chi ; et al.	2008-03-27
One-transistor random access memory technology compatible with metal gate process Grant 7,271,083 - Tu , et al. September 18, 2	2007-09-18
Embedded dual-port DRAM process Grant 7,091,543 - Tzeng , et al. August 15, 2	2006-08-15
One-transistor random access memory technology compatible with metal gate process App 20060017115 - Tu; Kuo-Chi ; et al.	2006-01-26
Novel embedded dual-port DRAM process App 20050017285 - Tzeng, Kuo-Chyuan ; et al.	2005-01-27
Embedded dual-port DRAM process Grant 6,794,254 - Tzeng , et al. September 21, 2	2004-09-21
Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices Grant 6,713,406 - Fu , et al. March 30, 2	2004-03-30
Single transistor random access memory (1T-RAM) cell with dual threshold voltages Grant 6,670,664 - Tzeng , et al. December 30, 2	2003-12-30
Memory cell structure with trench capacitor and method for fabrication thereof Grant 6,661,050 - Tzeng , et al. December 9, 2	2003-12-09
Microelectronic capacitor structure embedded within microelectronic isolation region Grant 6,661,049 - Tzeng , et al. December 9, 2	2003-12-09
Method of forming a composite spacer to eliminate polysilicon stringers between elements in a pseudo SRAM cell Grant 6,638,813 - Tzeng , et al. October 28, 2	2003-10-28
Memory Cell Structure With Trench Capacitor And Method For Fabrication Thereof App 20030178661 - Tzeng, Kuo-Chyuan ; et al.	2003-09-25
Method to integrate high performance 1T ram in a CMOS process using asymmetric structure Grant 6,620,679 - Tzeng , et al. September 16, 2	2003-09-16
Approach for forming a buried stack capacitor structure featuring reduced polysilicon stringers Grant 6,613,690 - Chang , et al. September 2, 2	2003-09-02
Microelectronic capacitor structure embedded within microelectronic isolation region App 20030042519 - Tzeng, Kuo-Chyuan ; et al.	2003-03-06
Method to define poly dog-bone for word line strapping contact at stitch area in embedded DRAM process Grant 6,376,294 - Tzeng , et al. April 23, 2	2002-04-23
Self-aligned etching method for forming high areal density patterned microelectronic structures Grant 6,306,767 - Tzeng , et al. October 23, 2	2001-10-23
Common gate and salicide word line process for low cost embedded DRAM devices Grant 6,207,492 - Tzeng , et al. March 27, 2	2001-03-27
Capacitor circuit structure for determining overlay error Grant 6,143,621 - Tzeng , et al. November 7, 2	2000-11-07

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