Tung; Chiayao S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tung; Chiayao S..The latest application filed is for "short circuits and power limit protection circuits".

Company Profile

0.13.1

Tung; Chiayao S. - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Current mode digitally variable resistor or programmable VCOM Grant 10,741,142 - Viviani , et al. A	2020-08-11
Current mode DVR or PVCOM with integrated impedances Grant 9,754,550 - Viviani , et al. September 5, 2	2017-09-05
Current mode DVR or PVCOM with integrated impedances Grant 9,548,723 - Viviani , et al. January 17, 2	2017-01-17
Short circuits and power limit protection circuits Grant 9,478,978 - Fu , et al. October 25, 2	2016-10-25
Current mode DVR or PVCOM with integrated impedances Grant 9,166,566 - Viviani , et al. October 20, 2	2015-10-20
Short circuits and power limit protection circuits Grant 9,054,527 - Fu , et al. June 9, 2	2015-06-09
Current mode DVR or PVCOM with integrated resistors Grant 9,007,098 - Viviani , et al. April 14, 2	2015-04-14
Short circuits and power limit protection circuits Grant 8,154,346 - Tung April 10, 2	2012-04-10
Short Circuits and Power Limit Protection Circuits App 20110115564 - Tung; Chiayao S.	2011-05-19
System and method for multi-symbol interfacing Grant 7,167,527 - Park , et al. January 23, 2	2007-01-23
Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle Grant 7,043,657 - Yang , et al. May 9, 2	2006-05-09
System and method for multi-symbol interfacing Grant 6,937,664 - Park , et al. August 30, 2	2005-08-30
Universal synchronization clock signal derived using single forward and reverse direction clock signals even when phase delay between both signals is greater than one cycle Grant 6,647,506 - Yang , et al. November 11, 2	2003-11-11
System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream Grant 6,477,592 - Chen , et al. November 5, 2	2002-11-05

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