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name:-0.040719032287598
name:-0.016592025756836
name:-0.0038130283355713
Tuncer; Emre Patent Filings

Tuncer; Emre

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tuncer; Emre.The latest application filed is for "leakage screening based on use-case power prediction".

Company Profile
3.16.18
  • Tuncer; Emre - Santa Cruz CA
  • Tuncer; Emre - Palo Alto CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Leakage Screening Based on Use-Case Power Prediction
App 20220268835 - Tuncer; Emre ;   et al.
2022-08-25
Generating Integrated Circuit Floorplans Using Neural Networks
App 20220043951 - Ho; Chian-min Richard ;   et al.
2022-02-10
Generating integrated circuit floorplans using neural networks
Grant 11,100,266 - Ho , et al. August 24, 2
2021-08-24
Voltage-Variation Detection Under Clock Fluctuations
App 20210148957 - Tuncer; Emre ;   et al.
2021-05-20
Generating Integrated Circuit Floorplans Using Neural Networks
App 20200364389 - Ho; Chian-min Richard ;   et al.
2020-11-19
Generating integrated circuit floorplans using neural networks
Grant 10,699,043 - Ho , et al.
2020-06-30
Generating Integrated Circuit Floorplans Using Neural Networks
App 20200175216 - Ho; Chian-min Richard ;   et al.
2020-06-04
Lithography aware leakage analysis
Grant 9,576,098 - Tuncer , et al. February 21, 2
2017-02-21
Lithography Aware Leakage Analysis
App 20140181762 - Tuncer; Emre ;   et al.
2014-06-26
Lithography aware leakage analysis
Grant 8,572,523 - Tuncer , et al. October 29, 2
2013-10-29
Variability-aware scheme for high-performance asynchronous circuit voltage regulation
Grant 8,572,539 - Cortadella , et al. October 29, 2
2013-10-29
Lithography aware timing analysis
Grant 8,473,876 - Tuncer , et al. June 25, 2
2013-06-25
Network of tightly coupled performance monitors for determining the maximum frequency of operation of a semiconductor IC
Grant 8,446,224 - Cortadella , et al. May 21, 2
2013-05-21
Network Of Tightly Coupled Performance Monitors For Determining The Maximum Frequency Of Operation Of A Semiconductor Ic
App 20120013408 - Cortadella; Jordi ;   et al.
2012-01-19
Variability-aware scheme for asynchronous circuit initialization
Grant 7,701,255 - Cortadella , et al. April 20, 2
2010-04-20
Variability-Aware Scheme for High-Performance Asynchronous Circuit Voltage Reglulation
App 20090115503 - Cortadella; Jordi ;   et al.
2009-05-07
Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols Using a Gated Latch Enable Scheme
App 20090115488 - Cortadella; Jordi ;   et al.
2009-05-07
Variability-Aware Asynchronous Scheme for Optimal-Performance Delay Matching
App 20090119621 - Cortadella; Jordi ;   et al.
2009-05-07
Variability-Aware Scheme for Asynchronous Circuit Initialization
App 20090115469 - Cortadella; Jordi ;   et al.
2009-05-07
Variability-Aware Asynchronous Scheme for High-Performance Communication Between an Asynchronous Circuit and a Synchronous Circuit
App 20090116597 - Cortadella; Jordi ;   et al.
2009-05-07
Variability-Aware Asynchronous Scheme for High-Performance Delay Matching
App 20090119631 - Cortadella; Jordi ;   et al.
2009-05-07
Variability-Aware Asynchronous Scheme Based on Two-Phase Protocols
App 20090119622 - Cortadella; Jordi ;   et al.
2009-05-07
Aggregate sensitivity for statistical static timing analysis
Grant 7,458,049 - Tuncer , et al. November 25, 2
2008-11-25
Lithography Aware Timing Analysis
App 20080052653 - Tuncer; Emre ;   et al.
2008-02-28
Lithography Aware Leakage Analysis
App 20080052646 - Tuncer; Emre ;   et al.
2008-02-28
Reduction of cross-talk noise in VLSI circuits
Grant 7,058,907 - Tuncer , et al. June 6, 2
2006-06-06
Sensitivity-current-based model for equivalent waveform propagation in the presence of noise for static timing analysis
App 20060112357 - Nazarian; Shahin ;   et al.
2006-05-25
Reduction of cross-talk noise in VLSI circuits
App 20040205678 - Tuncer, Emre ;   et al.
2004-10-14
System and method for concurrent buffer insertion and placement of logic gates
Grant 6,367,051 - Pileggi , et al. April 2, 2
2002-04-02
Method for design optimization using logical and physical information
Grant 6,286,128 - Pileggi , et al. September 4, 2
2001-09-04

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