Tuan; Tim

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tuan; Tim.The latest application filed is for "multi-die integrated circuit with data processing engine array".

Company Profile

6.47.5

Tuan; Tim - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Data processing engines with cascade connected cores Grant 11,443,091 - McColgan , et al. September 13, 2	2022-09-13
Programmable device having a data processing engine (DPE) array Grant 11,386,020 - Klein , et al. July 12, 2	2022-07-12
Multi-die Integrated Circuit With Data Processing Engine Array App 20220197846 - Noguera Serra; Juan J. ; et al.	2022-06-23
Data processing engine array architecture with memory tiles Grant 11,336,287 - Rodriguez , et al. May 17, 2	2022-05-17
Multi-port stream switch for stream interconnect network Grant 11,323,391 - McColgan , et al. May 3, 2	2022-05-03
Data processing engine array architecture with memory tiles Grant 11,296,707 - Rodriguez , et al. April 5, 2	2022-04-05
Multi-die Integrated Circuit With Data Processing Engine Array App 20220100691 - Noguera Serra; Juan J. ; et al.	2022-03-31
Multi-die integrated circuit with data processing engine array Grant 11,288,222 - Noguera Serra , et al. March 29, 2	2022-03-29
Activity-aware clock gating for switches Grant 11,223,351 - Kasibhatla , et al. January 11, 2	2022-01-11
Data processing engine arrangement in a device Grant 10,866,753 - Noguera Serra , et al. December 15, 2	2020-12-15
Core for a data processing engine in an integrated circuit Grant 10,747,531 - Langer , et al. A	2020-08-18
System-on-chip interface architecture Grant 10,635,622 - Bilski , et al.	2020-04-28
System-on-chip Interface Architecture App 20190303328 - Balski; Goran H.K. ; et al.	2019-10-03
Data Processing Engine Arrangement In A Device App 20190303033 - Noguera Serra; Juan J. ; et al.	2019-10-03
Method and apparatus for adaptively tuning an integrated circuit Grant 9,444,497 - Mohan , et al. September 13, 2	2016-09-13
Time-multiplexed, asynchronous device Grant 9,355,690 - Tuan May 31, 2	2016-05-31
Optimizing supply voltage and threshold voltage Grant 9,348,959 - Tuan May 24, 2	2016-05-24
Device specific configuration of operating voltage Grant 9,015,023 - Tuan , et al. April 21, 2	2015-04-21
Methods for identifying gating opportunities from a high-level language program and generating a hardware definition Grant 8,443,344 - Sundararajan , et al. May 14, 2	2013-05-14
Multiple sleep mode memory device Grant 8,411,527 - Tuan April 2, 2	2013-04-02
Programmable integrated circuit with voltage domains Grant 8,159,263 - Tuan , et al. April 17, 2	2012-04-17
Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product Grant 8,155,907 - Lesea , et al. April 10, 2	2012-04-10
High-level circuit architecture optimizer Grant 8,146,045 - Tuan March 27, 2	2012-03-27
Apparatus and method for the detection and compensation of integrated circuit performance variation Grant 8,130,027 - Tuan March 6, 2	2012-03-06
Disabling unused/inactive resources in an integrated circuit for static power reduction Grant 8,099,691 - Tuan , et al. January 17, 2	2012-01-17
Device Specific Configuration Of Operating Voltage App 20110276321 - Tuan; Tim ; et al.	2011-11-10
Power management with packaged multi-die integrated circuit Grant 7,992,020 - Tuan , et al. August 2, 2	2011-08-02
System and method for using reconfiguration ports for power management in integrated circuits Grant 7,973,556 - Noguera Serra , et al. July 5, 2	2011-07-05
Early power estimator for integrated circuits Grant 7,810,058 - Tuan October 5, 2	2010-10-05
Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity Grant 7,764,081 - Tuan , et al. July 27, 2	2010-07-27
Methods and structures for flexible power management in integrated circuits Grant 7,620,926 - Tuan November 17, 2	2009-11-17
Method and mechanism for controlling power consumption of an integrated circuit Grant 7,581,124 - Jacobson , et al. August 25, 2	2009-08-25
Disabling unused/inactive resources in programmable logic devices for static power reduction Grant 7,562,332 - Tuan , et al. July 14, 2	2009-07-14
Tuning programmable logic devices for low-power design implementation Grant 7,549,139 - Tuan , et al. June 16, 2	2009-06-16
Method and apparatus for leakage current reduction Grant 7,545,177 - Kao , et al. June 9, 2	2009-06-09
Regulating unused/inactive resources in programmable logic devices for static power reduction Grant 7,504,854 - Look , et al. March 17, 2	2009-03-17
Programmable low power modes for embedded memory blocks Grant 7,498,836 - Tuan March 3, 2	2009-03-03
Implementation of low power standby modes for integrated circuits Grant 7,498,835 - Rahman , et al. March 3, 2	2009-03-03
Power gating various number of resources based on utilization levels Grant 7,490,302 - Rahman , et al. February 10, 2	2009-02-10
Structures and methods for heterogeneous low power programmable logic device Grant 7,477,073 - Tuan , et al. January 13, 2	2009-01-13
Low-swing interconnections for field programmable gate arrays Grant 7,417,454 - Rahman , et al. August 26, 2	2008-08-26
Method and apparatus for a configurable latch Grant 7,253,661 - Tuan , et al. August 7, 2	2007-08-07
Method and apparatus for power optimization during an integrated circuit design process Grant 7,243,312 - Lysaght , et al. July 10, 2	2007-07-10
Structure and method for suppressing sub-threshold leakage in integrated circuits Grant 7,212,462 - Tuan May 1, 2	2007-05-01
Disabling unused/inactive resources in programmable logic devices for static power reduction Grant 7,098,689 - Tuan , et al. August 29, 2	2006-08-29
Place-and-route with power analysis Grant 6,950,998 - Tuan September 27, 2	2005-09-27