Tuan; Jeh-Fu
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tuan; Jeh-Fu.The latest application filed is for "methods for reducing post layout circuit simulation results".
- Tuan; Jeh-Fu - San Jose CA
- Tuan; Jeh-Fu - Saratoga CA
| Patent | Date |
|---|---|
| Layout migration with hierarchical scale and bias method Grant 9,262,571 - Tuan February 16, 2 | 2016-02-16 |
| Methods For Reducing Post Layout Circuit Simulation Results App 20150269297 - Tuan; Jeh-Fu | 2015-09-24 |
| Layout Migration With Hierarchical Scale And Bias Method App 20140380259 - Tuan; Jeh-Fu | 2014-12-25 |
| Concurrent Simulation System Using Graphic Processing Units (gpu) And Method Thereof App 20130226535 - Tuan; Jeh-Fu | 2013-08-29 |
| Transistor level circuit simulator using hierarchical data Grant 6,577,992 - Tcherniaev , et al. June 10, 2 | 2003-06-10 |
| Method and system for reliability analysis of CMOS VLSI circuits based on stage partitioning and node activities Grant 6,249,898 - Koh , et al. June 19, 2 | 2001-06-19 |
| Hierarchial power network simulation and analysis tool for reliability testing of deep submicron IC designs Grant 5,878,053 - Koh , et al. March 2, 1 | 1999-03-02 |
| Integrated circuit power net analysis through simulation Grant 5,872,952 - Tuan , et al. February 16, 1 | 1999-02-16 |
| SEC | 0001165904 | TUAN JEH FU |
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