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name:-0.015398025512695
name:-0.012171030044556
name:-0.00053691864013672
Tu; Wu-Chang Patent Filings

Tu; Wu-Chang

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tu; Wu-Chang.The latest application filed is for "stacked chip package structure with leadframe having inner leads with transfer pad".

Company Profile
0.10.15
  • Tu; Wu-Chang - Hsinchu TW
  • Tu; Wu Chang - Tainan County TW
  • Tu; Wu-Chang - Hsinchu city TW
  • Tu; Wu-Chang - Tainan TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Stacked chip package structure with leadframe having inner leads with transfer pad
Grant 8,207,603 - Shen , et al. June 26, 2
2012-06-26
Stacked chip package structure with leadframe having bus bar
Grant 8,169,061 - Shen , et al. May 1, 2
2012-05-01
IC package reducing wiring layers on substrate and its carrier
Grant 8,026,615 - Lin , et al. September 27, 2
2011-09-27
Stacked Chip Package Structure with Leadframe Having Inner Leads with Transfer Pad
App 20100314729 - SHEN; Geng-Shin ;   et al.
2010-12-16
Chip package having asymmetric molding
Grant 7,834,432 - Tu , et al. November 16, 2
2010-11-16
Stacked Chip Package Structure with Leadframe Having Bus Bar
App 20100264527 - SHEN; Geng-Shin ;   et al.
2010-10-21
Stacked Chip Package Structure with Leadframe Having Bus Bar
App 20100264530 - SHEN; Geng-Shin ;   et al.
2010-10-21
IC Package Reducing Wiring Layers on Substrate and Its Carrier
App 20100264540 - Lin; Hung Tsun ;   et al.
2010-10-21
Stacked chip package structure with leadframe having inner leads with transfer pad
Grant 7,816,771 - Shen , et al. October 19, 2
2010-10-19
Stacked chip package structure with leadframe having bus bar
Grant 7,786,595 - Shen , et al. August 31, 2
2010-08-31
IC package reducing wiring layers on substrate and its chip carrier
Grant 7,781,898 - Lin , et al. August 24, 2
2010-08-24
Chip-Stacked Package Structure with Leadframe Having Multi-Piece Bus Bar
App 20100006997 - SHEN; Geng-Shin ;   et al.
2010-01-14
Chip-stacked package structure having leadframe with multi-piece bus bar
Grant 7,615,853 - Shen , et al. November 10, 2
2009-11-10
Chip Package Having Asymmetric Molding
App 20090243056 - Tu; Wu-Chang ;   et al.
2009-10-01
Chip package having with asymmetric molding and turbulent plate downset design
Grant 7,576,416 - Tu , et al. August 18, 2
2009-08-18
High frequency IC package and method for fabricating the same
Grant 7,554,197 - Huang , et al. June 30, 2
2009-06-30
Chip package reducing wiring layers on substrate and its carrier
App 20080174031 - Lin; Hung-Tsun ;   et al.
2008-07-24
Stacked chip package structure with leadframe having inner leads with transfer pad
App 20080099896 - Shen; Geng-Shin ;   et al.
2008-05-01
Stacked chip package structure with leadframe having bus bar
App 20080061421 - Shen; Geng-Shin ;   et al.
2008-03-13
Chip-stacked package structure with leadframe having multi-piece bus bar
App 20080061412 - Shen; Geng-Shin ;   et al.
2008-03-13
Chip-stacked package structure for lead frame having bus bars with transfer pads
App 20080061411 - Shen; Geng-Shin ;   et al.
2008-03-13
High frequency IC package and method for fabricating the same
App 20070235871 - Huang; Hsiang-Ming ;   et al.
2007-10-11
Universal Chip Package Structure
App 20070228581 - Chou; Shih-Wen ;   et al.
2007-10-04
Chip package having asymmetric molding
App 20070085176 - Tu; Wu-Chang ;   et al.
2007-04-19
Universal chip package structure
App 20070080466 - Chou; Shih-Wen ;   et al.
2007-04-12

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