Tsutsui; Gen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsutsui; Gen.The latest application filed is for "bottom source/drain for fin field effect transistors".

Company Profile

33.35.37

Tsutsui; Gen - Glenmont NY
Tsutsui; Gen - Albany NY
Tsutsui; Gen - Delmar NY
Tsutsui; Gen - Kawasaki JP
Tsutsui; Gen - Kanagawa-shi JP
Tsutsui; Gen - Kanagawa N/A JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bottom Source/drain For Fin Field Effect Transistors App 20220173240 - Wu; Heng ; et al.	2022-06-02
Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT) Grant 11,282,962 - Zhou , et al. March 22, 2	2022-03-22
Bottom source/drain for fin field effect transistors Grant 11,276,781 - Wu , et al. March 15, 2	2022-03-15
Differing device characteristics on a single wafer by selective etch Grant 11,183,427 - Zhou , et al. November 23, 2	2021-11-23
Bottom Source/drain For Fin Field Effect Transistors App 20210328051 - Wu; Heng ; et al.	2021-10-21
Vertical Transport Field Effect Transistor With Bottom Source/drain App 20210226055 - Wu; Heng ; et al.	2021-07-22
Vertical transport field effect transistor with bottom source/drain Grant 11,056,588 - Wu , et al. July 6, 2	2021-07-06
Formation of stacked vertical transport field effect transistors Grant 11,037,905 - Wu , et al. June 15, 2	2021-06-15
Vertical Transport Field Effect Transistor With Bottom Source/drain App 20210104627 - Wu; Heng ; et al.	2021-04-08
Interface charge reduction for SiGe surface Grant 10,971,626 - Sadana , et al. April 6, 2	2021-04-06
Hybrid BEOL metallization utilizing selective reflection mask Grant 10,957,646 - Briggs , et al. March 23, 2	2021-03-23
Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS Grant 10,937,648 - Lee , et al. March 2, 2	2021-03-02
Semiconductor device with mitigated local layout effects Grant 10,892,181 - Zhou , et al. January 12, 2	2021-01-12
Formation Of Stacked Vertical Transport Field Effect Transistors App 20200343222 - WU; Heng ; et al.	2020-10-29
Threshold Voltage Adjustment From Oxygen Vacancy By Scavenge Metal Filling At Gate Cut (ct) App 20200287048 - Zhou; Huimei ; et al.	2020-09-10
Differing Device Characteristics On A Single Wafer By Selective Etch App 20200227322 - Zhou; Huimei ; et al.	2020-07-16
Method Of Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects App 20200203214 - Zhou; Huimei ; et al.	2020-06-25
Fin isolation to mitigate local layout effects Grant 10,685,866 - Zhou , et al.	2020-06-16
Differing device characteristics on a single wafer by selective etch Grant 10,679,901 - Zhou , et al.	2020-06-09
Hybrid Beol Metallization Utilizing Selective Reflection Mask App 20200176388 - BRIGGS; Benjamin D. ; et al.	2020-06-04
Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT) Grant 10,672,910 - Zhou , et al.	2020-06-02
Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effects Grant 10,658,224 - Zhou , et al.	2020-05-19
Gate Stack Designs for Analog and Logic Devices in Dual Channel Si/SiGe CMOS App 20200144057 - Lee; Choonghyun ; et al.	2020-05-07
Fin Isolation To Mitigate Local Layout Effects App 20200083088 - Zhou; Huimei ; et al.	2020-03-12
Fin Oxidation By Flowable Oxide Fill And Steam Anneal To Mitigate Local Layout Effects App 20200083089 - Zhou; Huimei ; et al.	2020-03-12
Hybrid BEOL metallization utilizing selective reflection mask Grant 10,586,767 - Briggs , et al.	2020-03-10
Differing Device Characteristics On A Single Wafer By Selective Etch App 20200058555 - Zhou; Huimei ; et al.	2020-02-20
Threshold Voltage Adjustment From Oxygen Vacancy By Scavenge Metal Filling At Gate Cut (ct) App 20200052125 - Zhou; Huimei ; et al.	2020-02-13
Hybrid Beol Metallization Utilizing Selective Reflection Mask App 20200027840 - BRIGGS; Benjamin D. ; et al.	2020-01-23
FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation Grant 10,535,773 - Guo , et al. Ja	2020-01-14
Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOS Grant 10,535,517 - Lee , et al. Ja	2020-01-14
Interface Charge Reduction for SiGe Surface App 20190326429 - Sadana; Devendra ; et al.	2019-10-24
Gate Stack Designs for Analog and Logic Devices in Dual Channel Si/SiGe CMOS App 20190295844 - Lee; Choonghyun ; et al.	2019-09-26
Interface charge reduction for SiGe surface Grant 10,381,479 - Sadana , et al. A	2019-08-13
Semiconductor device including fin having condensed channel region Grant 10,319,811 - He , et al.	2019-06-11
Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared pFET and nFET trench Grant 10,312,245 - Liu , et al.	2019-06-04
Finfet With Sigma Recessed Source/drain And Un-doped Buffer Layer Epitaxy For Uniform Junction Formation App 20190157457 - Guo; Dechao ; et al.	2019-05-23
Self-aligned doping in source/drain regions for low contact resistance Grant 10,249,542 - Guo , et al.	2019-04-02
FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation Grant 10,249,758 - Guo , et al.	2019-04-02
Enabling low resistance gates and contacts integrated with bilayer dielectrics Grant 10,204,828 - Bao , et al. Feb	2019-02-12
Interface Charge Reduction for SiGe Surface App 20190035923 - Sadana; Devendra ; et al.	2019-01-31
Laser Spike Annealing For Solid Phase Epitaxy And Low Contact Resistance In An Sram With A Shared Pfet And Nfet Trench App 20190019796 - LIU; ZUOGUANG ; et al.	2019-01-17
Forming MOSFET structures with work function modification Grant 10,170,477 - Bao , et al. J	2019-01-01
Finfet With Sigma Recessed Source/drain And Un-doped Buffer Layer Epitaxy For Uniform Junction Formation App 20180358465 - Guo; Dechao ; et al.	2018-12-13
Forming MOSFET structures with work function modification Grant 10,147,725 - Bao , et al. De	2018-12-04
Laser Spike Annealing For Solid Phase Epitaxy And Low Contact Resistance In An Sram With A Shared Pfet And Nfet Trench App 20180315761 - Liu; Zuoguang ; et al.	2018-11-01
Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET trench Grant 10,115,728 - Liu , et al. October 30, 2	2018-10-30
FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation Grant 10,096,713 - Guo , et al. October 9, 2	2018-10-09
Self-aligned doping in source/drain regions for low contact resistance Grant 10,032,679 - Guo , et al. July 24, 2	2018-07-24
Self-aligned Doping In Source/drain Regions For Low Contact Resistance App 20180197792 - Guo; Dechao ; et al.	2018-07-12
Self-aligned Doping In Source/drain Regions For Low Contact Resistance App 20180197793 - Guo; Dechao ; et al.	2018-07-12
Semiconductor device and method of manufacturing the semiconductor device Grant 9,812,556 - Mochizuki , et al. November 7, 2	2017-11-07
Cutting fins and gates in CMOS devices Grant 9,721,848 - Bu , et al. August 1, 2	2017-08-01
Forming Mosfet Structures With Work Function Modification App 20170133372 - BAO; RUQIANG ; et al.	2017-05-11
Forming Mosfet Structures With Work Function Modification App 20170133272 - BAO; RUQIANG ; et al.	2017-05-11
Semiconductor Device Including Fin Having Condensed Channel Region App 20170033184 - He; Hong ; et al.	2017-02-02
Semiconductor Device Including Fin Having Condensed Channel Region App 20170033219 - He; Hong ; et al.	2017-02-02
Semiconductor Device And Method Of Manufacturing The Semiconductor Device App 20140183605 - Mochizuki; Shogo ; et al.	2014-07-03
Reducing gate resistance in nonplanar multi-gate transistor Grant 8,604,546 - Bryant , et al. December 10, 2	2013-12-10
Semiconductor device and method of manufacturing the semiconductor device Grant 8,586,437 - Iwamoto , et al. November 19, 2	2013-11-19
Semiconductor Device And Method Of Manufacturing The Semiconductor Device App 20120315736 - Iwamoto; Toshiyuki ; et al.	2012-12-13
Hybrid planarFET and FinFET provided on a chip Grant 8,269,271 - Iwamoto , et al. September 18, 2	2012-09-18
Method of manufacturing semiconductor device, and semiconductor device Grant 8,088,677 - Tsutsui January 3, 2	2012-01-03
Semiconductor device and method of manufacturing the semiconductor device App 20100270621 - Iwamoto; Toshiyuki ; et al.	2010-10-28
Semiconductor Device App 20100224914 - IWAMOTO; Toshiyuki ; et al.	2010-09-09
Semiconductor device and method of manufacturing the same App 20100123200 - Tsutsui; Gen	2010-05-20
Semiconductor Device And Method Of Manufacturing Semiconductor Device App 20100117156 - TSUTSUI; Gen ; et al.	2010-05-13
Method of manufacturing semiconductor device, and semiconductor device App 20100013017 - Tsutsui; Gen	2010-01-21
Semiconductor device and method of manufacturing the same App 20100001352 - Tsutsui; Gen ; et al.	2010-01-07
Semiconductor Device And Method Of Manufacturing The Same App 20080093699 - ABE; Tomohisa ; et al.	2008-04-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.