Tsu; Robert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsu; Robert.The latest application filed is for "line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer".

Company Profile

0.16.6

Tsu; Robert - Plano TX
Tsu; Robert - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer Grant 7,402,514 - Tsu , et al. July 22, 2	2008-07-22
Copper transition layer for improving copper interconnection reliability Grant 6,951,812 - Jiang , et al. October 4, 2	2005-10-04
Line-to-line reliability enhancement using a dielectric liner for a low dielectric constant interlevel and intralevel (or intermetal and intrametal) dielectric layer App 20040147112 - Tsu, Robert ; et al.	2004-07-29
Copper transition layer for improving copper interconnection reliability App 20040132282 - Jiang, Qing-Tang ; et al.	2004-07-08
Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region Grant 6,696,337 - Asano , et al. February 24, 2	2004-02-24
Copper transition layer for improving copper interconnection reliability Grant 6,693,356 - Jiang , et al. February 17, 2	2004-02-17
Integrated circuit capacitor Grant 6,653,676 - Tsu , et al. November 25, 2	2003-11-25
Copper transition layer for improving copper interconnection reliability App 20030186543 - Jiang, Qing-Tang ; et al.	2003-10-02
Method of manufacturing a semiconductor integrated circuit device having a memory cell array and a peripheral circuit region App 20020155662 - Asano, Isamu ; et al.	2002-10-24
Yield improvement of dual damascene fabrication through oxide filling Grant 6,461,955 - Tsu , et al. October 8, 2	2002-10-08
Hole-type storage cell structure and method for making the structure App 20020043681 - Tsu, Robert ; et al.	2002-04-18
Integrated circuit capacitor App 20020014646 - Tsu, Robert ; et al.	2002-02-07
Integrated circuit capacitor Grant 6,294,420 - Tsu , et al. September 25, 2	2001-09-25
Semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity and method of manufacturing same Grant 6,168,985 - Asano , et al. January 2, 2	2001-01-02
Method for fabricating an integrated circuit structure Grant 6,096,597 - Tsu , et al. August 1, 2	2000-08-01
Method of manufacturing semiconductor integrated circuit device including a DRAM having reduced parasitic bit line capacity Grant 6,037,207 - Asano , et al. March 14, 2	2000-03-14
Method of making barium strontium titanate (BST) thin film by erbium donor doping Grant 5,731,220 - Tsu , et al. March 24, 1	1998-03-24
Barium strontium titanate (BST) thin films by erbium donor doping Grant 5,635,741 - Tsu , et al. June 3, 1	1997-06-03
Barium strontium titanate (BST) thin films using boron Grant 5,617,290 - Kulwicki , et al. April 1, 1	1997-04-01
Processing methods for high-dielectric-constant materials Grant 5,609,927 - Summerfelt , et al. March 11, 1	1997-03-11
Barium strontium titanate (BST) thin films by holmium donor doping Grant 5,453,908 - Tsu , et al. September 26, 1	1995-09-26
Reliability enhancement of aluminum interconnects by reacting aluminum leads with a strengthening gas Grant 5,432,128 - Tsu July 11, 1	1995-07-11

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