Tseng; Jui-Hsing

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tseng; Jui-Hsing.The latest application filed is for "electronic system and related method with time-sharing bus".

Company Profile

0.9.9

Tseng; Jui-Hsing - Hsinchu County TW
Tseng; Jui-Hsing - Kaohsiung TW
Tseng; Jui-Hsing - Hsin-Chu Hsien TW
Tseng; Jui-Hsing - Kaoshiung TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory control methods capable of dynamically adjusting sampling points, and related circuits Grant 7,876,629 - Tseng January 25, 2	2011-01-25
Memory control circuit capable of dynamically adjusting deglitch windows, and related method Grant 7,778,093 - Tseng August 17, 2	2010-08-17
Methods and systems for generating latch clock used in memory reading Grant 7,652,938 - Tseng January 26, 2	2010-01-26
Electronic System And Related Method With Time-sharing Bus App 20090319708 - Ho; Yu-Ping ; et al.	2009-12-24
Memory controllers and pad sequence control methods thereof Grant 7,561,481 - Chen , et al. July 14, 2	2009-07-14
Memory Control Circuit Capable Of Dynamically Adjusting Deglitch Windows, And Related Method App 20090043981 - Tseng; Jui-Hsing	2009-02-12
Memory Control Methods Capable Of Dynamically Adjusting Sampling Points, And Related Circuits App 20090043953 - Tseng; Jui-Hsing	2009-02-12
Memory Controllers And Pad Sequence Control Methods Thereof App 20080304352 - Chen; Nan-Cheng ; et al.	2008-12-11
Memory system comprising memories with different capacities and storing and reading method thereof Grant 7,394,715 - Tseng July 1, 2	2008-07-01
Systems and methods for automatically eliminating imbalance between signals Grant 7,362,107 - Tseng , et al. April 22, 2	2008-04-22
Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof Grant 7,236,027 - Tseng June 26, 2	2007-06-26
Systems And Methods For Automatically Eliminating Imbalance Between Signals App 20070118251 - Tseng; Jui-Hsing ; et al.	2007-05-24
Methods And Systems For Generating Latch Clock Used In Memory Reading App 20070041253 - Tseng; Jui-Hsing	2007-02-22
Jitter-resistive Delay Lock Loop Circuit For Locking Delayed Clock And Method Thereof App 20060290394 - Tseng; Jui-Hsing	2006-12-28
Methods and systems for generating latch clock used in memory reading Grant 7,142,470 - Tseng November 28, 2	2006-11-28
Jitter-resistive delay lock loop circuit for locking delayed clock and method thereof Grant 7,119,589 - Tseng October 10, 2	2006-10-10
Methods and systems for generating latch clock used in memory reading App 20060215466 - Tseng; Jui-Hsing	2006-09-28
Jitter-resistive Delay Lock Loop Circuit For Locking Delayed Clock And Method Thereof App 20060055440 - Tseng; Jui-Hsing	2006-03-16

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