Tsao; Jenn

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsao; Jenn.The latest application filed is for "method of fabricating buried source to shrink chip size in memory array".

Company Profile

0.8.1

Tsao; Jenn - Town Taoyuan TW
Tsao, Jenn - Taipei TW
Tsao; Jenn - Taoyuan TW
Tsao; Jenn - Yungmei Town TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low inductance connector with enhanced capacitively coupled contacts for power applications Grant 6,358,094 - Belopolsky , et al. March 19, 2	2002-03-19
Method of fabricating buried source to shrink chip size in memory array App 20010017387 - Hsieh, Chia-Ta ; et al.	2001-08-30
Method of fabricating buried source to shrink chip size in memory array Grant 6,207,515 - Hsieh , et al. March 27, 2	2001-03-27
Method for forming a shallow trench isolation structure Grant 6,136,713 - Chen , et al. October 24, 2	2000-10-24
Stacked double deck modular gang jack connector Grant 6,080,011 - Tsao , et al. June 27, 2	2000-06-27
Method of fabricating buried source to shrink cell dimension and increase coupling ratio in split-gate flash Grant 6,017,795 - Hsieh , et al. January 25, 2	2000-01-25
Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC) Grant 5,817,562 - Chang , et al. October 6, 1	1998-10-06
Process for integrating a MOSFET device, using silicon nitride spacers and a self-aligned contact structure, with a capacitor structure Grant 5,766,992 - Chou , et al. June 16, 1	1998-06-16
Filtered modular jack assembly and method of use Grant 5,456,619 - Belopolsky , et al. October 10, 1	1995-10-10

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