Tsao; Hsing-Ya

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsao; Hsing-Ya.The latest application filed is for "1t1b and 2t2b flash-based, data-oriented eeprom design".

Company Profile

0.68.45

Tsao; Hsing-Ya - San Jose CA US
Tsao, Hsing-Ya - Santa Clara CA
Tsao; Hsing-Ya - Taipei TW
Tsao; Hsing-Ya - Hsin-Chu TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low-voltage fast-write PMOS NVSRAM cell Grant 9,177,644 - Tsao , et al. November 3, 2	2015-11-03
1T1b and 2T2b flash-based, data-oriented EEPROM design Grant 9,177,658 - Lee , et al. November 3, 2	2015-11-03
10T NVSRAM cell and cell operations Grant 9,177,645 - Tsao , et al. November 3, 2	2015-11-03
Non-boosting program inhibit scheme in NAND design Grant 9,171,627 - Lee , et al. October 27, 2	2015-10-27
Low-voltage page buffer to be used in NVM design Grant 9,019,764 - Lee , et al. April 28, 2	2015-04-28
On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation Grant 9,001,583 - Lee , et al. April 7, 2	2015-04-07
1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN App 20150071007 - Lee; Peter Wung ; et al.	2015-03-12
8T NVSRAM cell and cell operations Grant 8,929,136 - Lee , et al. January 6, 2	2015-01-06
1T1b and 2T2b flash-based, data-oriented EEPROM design Grant 8,923,049 - Lee , et al. December 30, 2	2014-12-30
8t Nvsram Cell And Cell Operations App 20140119118 - Lee; Peter Wung ; et al.	2014-05-01
10t Nvsram Cell And Cell Operations App 20140112072 - Tsao; Hsing-Ya ; et al.	2014-04-24
On-chip Hv And Lv Capacitors Acting As The Second Back-up Supplies For Nvsram Auto-store Operation App 20140104946 - Lee; Peter Wung ; et al.	2014-04-17
Low-voltage Fast-write Pmos Nvsram Cell App 20140050025 - Tsao; Hsing-Ya ; et al.	2014-02-20
Universal timing waveforms sets to improve random access read and write speed of memories Grant 8,634,241 - Lee , et al. January 21, 2	2014-01-21
Low-voltage Fast-write Nvsram Cell App 20130294161 - Lee; Peter Wung ; et al.	2013-11-07
Non-boosting Program Inhibit Scheme In Nand Design App 20130272067 - Lee; Peter Wung ; et al.	2013-10-17
Three-Dimensional Flash-Based Combo Memory and Logic Design App 20130215683 - Lee; Peter Wung ; et al.	2013-08-22
NEW 1T1b AND 2T2b FLASH-BASED, DATA-ORIENTED EEPROM DESIGN App 20130182509 - Lee; Peter Wung ; et al.	2013-07-18
Low-Voltage Page Buffer to be Used in NVM Design App 20130128667 - Lee; Peter Wung ; et al.	2013-05-23
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array Grant 8,345,481 - Lee , et al. January 1, 2	2013-01-01
Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/- 10v BVDS Grant 8,295,087 - Lee , et al. October 23, 2	2012-10-23
Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array Grant 8,289,775 - Lee , et al. October 16, 2	2012-10-16
Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS Grant 8,274,829 - Lee , et al. September 25, 2	2012-09-25
Nonvolatile memory with a unified cell structure Grant 8,237,212 - Lee , et al. August 7, 2	2012-08-07
Universal Timing Waveforms Sets to Improve Random Access Read and Write Speed of Memories App 20120155173 - LEE; Peter Wung ; et al.	2012-06-21
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS flash memory array App 20120044770 - Lee; Peter Wung ; et al.	2012-02-23
NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array Grant 8,072,811 - Lee , et al. December 6, 2	2011-12-06
Nonvolatile Memory With A Unified Cell Structure App 20110170357 - Lee; Peter W. ; et al.	2011-07-14
Nonvolatile memory with a unified cell structure Grant 7,915,092 - Lee , et al. March 29, 2	2011-03-29
Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array App 20090316487 - Lee; Peter Wung ; et al.	2009-12-24
Nonvolatile memory with a unified cell structure Grant 7,636,252 - Lee , et al. December 22, 2	2009-12-22
Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/- 10V BVDS App 20090310411 - Lee; Peter Wung ; et al.	2009-12-17
Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/-10v BVDS App 20090310405 - Lee; Peter Wung ; et al.	2009-12-17
NAND based NMOS NOR flash memory cell, a NAND based NMOS nor flash memory array, and a method of forming a NAND based NMOS NOR flash memory array App 20090279360 - Lee; Peter Wung ; et al.	2009-11-12
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20080247230 - Lee; Peter W. ; et al.	2008-10-09
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,372,736 - Lee , et al. May 13, 2	2008-05-13
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20080096327 - Lee; Peter W. ; et al.	2008-04-24
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations Grant 7,349,257 - Lee , et al. March 25, 2	2008-03-25
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations Grant 7,339,824 - Lee , et al. March 4, 2	2008-03-04
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,324,384 - Lee , et al. January 29, 2	2008-01-29
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,289,366 - Lee , et al. October 30, 2	2007-10-30
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,283,401 - Lee , et al. October 16, 2	2007-10-16
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations App 20070133341 - Lee; Peter W. ; et al.	2007-06-14
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations App 20070076480 - Lee; Peter W. ; et al.	2007-04-05
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20070047302 - Lee; Peter W. ; et al.	2007-03-01
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations Grant 7,154,783 - Lee , et al. December 26, 2	2006-12-26
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations Grant 7,149,120 - Lee , et al. December 12, 2	2006-12-12
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20060234394 - Lee; Peter W. ; et al.	2006-10-19
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,120,064 - Lee , et al. October 10, 2	2006-10-10
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,110,302 - Lee , et al. September 19, 2	2006-09-19
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,102,929 - Lee , et al. September 5, 2	2006-09-05
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20060176739 - Lee; Peter W. ; et al.	2006-08-10
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20060176738 - Lee; Peter W. ; et al.	2006-08-10
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20060171203 - Lee; Peter W. ; et al.	2006-08-03
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,075,826 - Lee , et al. July 11, 2	2006-07-11
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout Grant 7,064,978 - Lee , et al. June 20, 2	2006-06-20
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations App 20050185501 - Lee, Peter W. ; et al.	2005-08-25
Novel EEPROM cell structure and array architecture App 20050169052 - Hsu, Fu-Chang ; et al.	2005-08-04
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20050162910 - Lee, Peter W. ; et al.	2005-07-28
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations App 20050141298 - Lee, Peter W. ; et al.	2005-06-30
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20050135152 - Lee, Peter W. ; et al.	2005-06-23
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20050128805 - Lee, Peter ; et al.	2005-06-16
EEPROM cell structure and array architecture Grant 6,906,376 - Hsu , et al. June 14, 2	2005-06-14
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20050122776 - Lee, Peter W. ; et al.	2005-06-09
Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write With No Disturb And Divided-well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder And Layout Grant 6,862,223 - Lee , et al. March 1, 2	2005-03-01
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations Grant 6,850,438 - Lee , et al. February 1, 2	2005-02-01
Set of three level concurrent word line bias conditions for a NOR type flash memory array Grant 6,818,491 - Lee , et al. November 16, 2	2004-11-16
Flash memory array structure suitable for multiple simultaneous operations Grant 6,788,611 - Hsu , et al. September 7, 2	2004-09-07
Flash memory array structure suitable for multiple simultaneous operations Grant 6,788,612 - Hsu , et al. September 7, 2	2004-09-07
Set of three level concurrent word line bias conditions for a NOR type flash memory array Grant 6,777,292 - Lee , et al. August 17, 2	2004-08-17
Two transistor flash memory cell for use in EEPROM arrays with a programmable logic device Grant 6,757,196 - Tsao , et al. June 29, 2	2004-06-29
Parallel channel programming scheme for MLC flash memory Grant 6,714,457 - Hsu , et al. March 30, 2	2004-03-30
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout App 20040047203 - Lee, Peter W. ; et al.	2004-03-11
Novel set of three level concurrent word line bias conditions for a NOR type flash memory array App 20040027894 - Lee, Peter W. ; et al.	2004-02-12
Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operations App 20040027856 - Lee, Peter W. ; et al.	2004-02-12
Novel set of three level concurrent word line bias conditions for a NOR type flash memory array App 20040029335 - Lee, Peter W. ; et al.	2004-02-12
Stacked gate flash memory cell with reduced distrub conditions App 20040008561 - Lee, Peter W. ; et al.	2004-01-15
Stacked gate flash memory cell with reduced disturb conditions Grant 6,660,585 - Lee , et al. December 9, 2	2003-12-09
Novel flash memory array structure suitable for multiple simultaneous operations App 20030206455 - Hsu, Fu-Chang ; et al.	2003-11-06
Novel flash memory array structure suitable for multiple simultaneous operations App 20030206456 - Hsu, Fu-Chang ; et al.	2003-11-06
Flash memory array for multiple simultaneous operations Grant 6,628,563 - Hsu , et al. September 30, 2	2003-09-30
Set of three level concurrent word line bias conditions for a nor type flash memory array Grant 6,620,682 - Lee , et al. September 16, 2	2003-09-16
3-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cell Grant 6,556,481 - Hsu , et al. April 29, 2	2003-04-29
Bit-by-bit Vt-correction operation for nonvolatile semiconductor one-transistor cell, nor-type flash EEPROM Grant 6,515,910 - Lee , et al. February 4, 2	2003-02-04
Three step write process used for a nonvolatile NOR type EEPROM memory Grant 6,498,752 - Hsu , et al. December 24, 2	2002-12-24
Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation Grant 6,381,670 - Lee , et al. April 30, 2	2002-04-30
Erase condition for flash memory Grant 6,134,150 - Hsu , et al. October 17, 2	2000-10-17
Positive/negative high voltage charge pump system Grant 6,023,188 - Lee , et al. February 8, 2	2000-02-08
Node-precise voltage regulation for a MOS memory system Grant 6,009,022 - Lee , et al. December 28, 1	1999-12-28
Charge pump circuits Grant 5,978,283 - Hsu , et al. November 2, 1	1999-11-02
Flash memory protection attribute status bits held in a flash memory array Grant 5,930,826 - Lee , et al. July 27, 1	1999-07-27
Flash memory with novel bitline decoder and sourceline latch Grant 5,920,503 - Lee , et al. July 6, 1	1999-07-06
Flash memory with high speed erasing structure using thin oxide semiconductor devices Grant 5,917,757 - Lee , et al. June 29, 1	1999-06-29
Flash memory with high speed erasing structure using thin oxide and thick oxide semiconductor devices Grant 5,914,896 - Lee , et al. June 22, 1	1999-06-22
Flash memory address decoder with novel latch structure Grant 5,848,000 - Lee , et al. December 8, 1	1998-12-08
Flash memory wordline decoder with overerase repair Grant 5,822,252 - Lee , et al. October 13, 1	1998-10-13
Flash memory with flexible erasing size from multi-byte to multi-block Grant 5,796,657 - Lee , et al. August 18, 1	1998-08-18
Flash memory array and decoding architecture Grant 5,777,924 - Lee , et al. July 7, 1	1998-07-07
Flash memory read/write controller Grant 5,777,923 - Lee , et al. July 7, 1	1998-07-07
Bit-refreshable method and circuit for refreshing a nonvolatile flash memory Grant 5,768,193 - Lee , et al. June 16, 1	1998-06-16
Memory device with on-chip manufacturing and memory cell defect detection capability Grant 5,748,545 - Lee , et al. May 5, 1	1998-05-05
OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array Grant 5,748,538 - Lee , et al. May 5, 1	1998-05-05
Flash EEPROM worldline decoder Grant 5,687,121 - Lee , et al. November 11, 1	1997-11-11
Flash memory with divided bitline Grant 5,682,350 - Lee , et al. October 28, 1	1997-10-28
Flexible byte-erase flash memory and decoder Grant 5,646,890 - Lee , et al. July 8, 1	1997-07-08