loadpatents
name:-0.015377044677734
name:-0.012645959854126
name:-0.0013339519500732
Tsao; Alwin Patent Filings

Tsao; Alwin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsao; Alwin.The latest application filed is for "variable implant and wafer-level feed-forward for dopant dose optimization".

Company Profile
1.11.12
  • Tsao; Alwin - Garland TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Variable implant and wafer-level feed-forward for dopant dose optimization
Grant 11,455,452 - Nandakumar , et al. September 27, 2
2022-09-27
Variable Implant And Wafer-level Feed-forward For Dopant Dose Optimization
App 20210089694 - Nandakumar; Mahalingam ;   et al.
2021-03-25
High tilt angle plus twist drain extension implant for CHC lifetime improvement
Grant 9,431,248 - Bo , et al. August 30, 2
2016-08-30
High Tilt Angle Plus Twist Drain Extension Implant For Chc Lifetime Improvement
App 20160027647 - Bo; Xiang-Zheng ;   et al.
2016-01-28
High tilt angle plus twist drain extension implant for CHC lifetime improvement
Grant 9,177,802 - Bo , et al. November 3, 2
2015-11-03
High Tilt Angle Plus Twist Drain Extension Implant For Chc Lifetime Improvement
App 20140187008 - Bo; Xiang-Zheng ;   et al.
2014-07-03
Application of different isolation schemes for logic and embedded memory
Grant 8,067,279 - Sadra , et al. November 29, 2
2011-11-29
Application of different isolation schemes for logic and embedded memory
Grant 7,662,688 - Sadra , et al. February 16, 2
2010-02-16
Application of Different Isolation Schemes for Logic and Embedded Memory
App 20090258471 - Sadra; Kayvan ;   et al.
2009-10-15
Application of Different Isolation Schemes for Logic and Embedded Memory
App 20080003772 - Sadra; Kayvan ;   et al.
2008-01-03
Application of different isolation schemes for logic and embedded memory
Grant 7,314,800 - Sadra , et al. January 1, 2
2008-01-01
Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode
Grant 7,250,334 - Crenshaw , et al. July 31, 2
2007-07-31
Method to Reduce Transistor Gate to Source/Drain Overlap Capacitance by Incorporation of Carbon
App 20070166906 - Mansoori; Majid Movahed ;   et al.
2007-07-19
Method to reduce transistor gate to source/drain overlap capacitance by incorporation of carbon
Grant 7,199,011 - Mansoori , et al. April 3, 2
2007-04-03
Application of different isolation schemes for logic and embedded memory
Grant 7,193,277 - Sadra , et al. March 20, 2
2007-03-20
Application of different isolation schemes for logic and embedded memory
Grant 7,141,468 - Sadra , et al. November 28, 2
2006-11-28
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)
Grant 7,045,436 - Chatterjee , et al. May 16, 2
2006-05-16
Application of different isolation schemes for logic and embedded memory
App 20060084230 - Sadra; Kayvan ;   et al.
2006-04-20
Metal insulator metal (MIM) capacitor fabrication with sidewall spacers and aluminum cap (ALCAP) top electrode
App 20060024899 - Crenshaw; Darius L. ;   et al.
2006-02-02
Method to engineer the inverse narrow width effect (INWE) in CMOS technology using shallow trench isolation (STI)
App 20060024910 - Chatterjee; Amitava ;   et al.
2006-02-02
Application of different isolation schemes for logic and embedded memory
App 20050145949 - Sadra, Kayvan ;   et al.
2005-07-07
Application of different isolation schemes for logic and embedded memory
App 20050087810 - Sadra, Kayvan ;   et al.
2005-04-28
Method to reduce transistor gate to source/drain overlap capacitance by incorporaton of carbon
App 20050014353 - Mansoori, Majid Movahed ;   et al.
2005-01-20

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