| Patent | Date |
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Standard Cell And Semiconductor Device Including Anchor Nodes And Method Of Making
App 20210365623 - TSAI; Nien-Yu ; et al. | 2021-11-25 |
Multi-patterning Graph Reduction And Checking Flow Method
App 20210279398 - TSAI; Nien-Yu ; et al. | 2021-09-09 |
Standard cell and semiconductor device including anchor nodes and method of making
Grant 11,106,852 - Tsai , et al. August 31, 2 | 2021-08-31 |
Multi-patterning graph reduction and checking flow method
Grant 11,017,148 - Tsai , et al. May 25, 2 | 2021-05-25 |
Standard Cell And Semiconductor Device Including Anchor Nodes And Method Of Making
App 20200311333 - TSAI; Nien-Yu ; et al. | 2020-10-01 |
Standard cell and semiconductor device including anchor nodes
Grant 10,713,407 - Tsai , et al. | 2020-07-14 |
Multi-patterning Graph Reduction And Checking Flow Method
App 20200167519 - TSAI; Nien-Yu ; et al. | 2020-05-28 |
Multi-patterning graph reduction and checking flow method
Grant 10,430,544 - Tsai , et al. O | 2019-10-01 |
Standard Cell And Semiconductor Device Including Anchor Nodes
App 20190130061 - TSAI; Nien-Yu ; et al. | 2019-05-02 |
Method of designing a semiconductor device, system for implementing the method and standard cell
Grant 10,162,928 - Tsai , et al. Dec | 2018-12-25 |
Methods of manufacturing a semiconductor device
Grant 10,121,694 - Chang , et al. November 6, 2 | 2018-11-06 |
Multi-patterning Graph Reduction And Checking Flow Method
App 20180068049 - TSAI; Nien-Yu ; et al. | 2018-03-08 |
Method Of Designing A Semiconductor Device, System For Implementing The Method And Standard Cell
App 20170161424 - TSAI; Nien-Yu ; et al. | 2017-06-08 |
Method and system of determining colorability of a layout
Grant 9,514,266 - Tsai , et al. December 6, 2 | 2016-12-06 |
Method Of Determining Colorability Of A Layout And System For Implementing The Same
App 20160063169 - TSAI; Nien-Yu ; et al. | 2016-03-03 |
Methods Of Manufacturing A Semiconductor Device
App 20160035615 - Chang; Yu-Jung ; et al. | 2016-02-04 |
DRC format for stacked CMOS design
Grant 9,038,010 - Chuang , et al. May 19, 2 | 2015-05-19 |
Drc Format For Stacked Cmos Design
App 20150113489 - Chuang; Yao-Jen ; et al. | 2015-04-23 |
Semiconductor hole structure
Grant 8,895,447 - Tsai , et al. November 25, 2 | 2014-11-25 |
Semiconductor Hole Structure
App 20140070373 - Tsai; Nien-Yu ; et al. | 2014-03-13 |
Structure And Manufacturing Method For Reducing Stress Of Chip
App 20130214424 - TSAI; Nien-Yu ; et al. | 2013-08-22 |
Method of planarizing spin-on material layer and manufacturing photoresist layer
Grant 6,998,277 - Lu , et al. February 14, 2 | 2006-02-14 |
Method Of Planarizing Spin-on Material Layerand Manufacturing Photoresist Layer
App 20050196879 - Lu, Jefferson ; et al. | 2005-09-08 |
Method for etching a trench through an anti-reflective coating
Grant 6,743,726 - Lu , et al. June 1, 2 | 2004-06-01 |
Method of reducing wafer etching defect
App 20040067654 - Chen, Chun-Wei ; et al. | 2004-04-08 |
Method for etching a trench through an anti-reflective coating
App 20040009672 - Lu, Jefferson ; et al. | 2004-01-15 |
Method for forming gate structure
App 20030059996 - Tsai, Nien-Yu ; et al. | 2003-03-27 |
Method for controlling etching depth
App 20020142613 - Fu, Ching-Hung ; et al. | 2002-10-03 |
Method of forming tungsten interconnect and vias without tungsten loss during wet stripping of photoresist polymer
Grant 6,410,417 - Tsai , et al. June 25, 2 | 2002-06-25 |
Etching Gas For Silicon Etch Back
App 20020066884 - TSAI, NIEN-YU ; et al. | 2002-06-06 |
Deep trench bottle-shaped etching using Cl2 gas
Grant 6,306,772 - Lin , et al. October 23, 2 | 2001-10-23 |
Method of forming tungsten interconnect with tungsten oxidation to prevent tungsten loss
Grant 6,143,653 - Tsai , et al. November 7, 2 | 2000-11-07 |
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