loadpatents
Patent applications and USPTO patent grants for Tsai; Min-Hsiu.The latest application filed is for "apparatus for adjusting skew of circuit signal and adjusting method thereof".
Patent | Date |
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Driving mechanism Grant 11,422,334 - Fu , et al. August 23, 2 | 2022-08-23 |
Optical element driving mechanism Grant 11,409,069 - Hu , et al. August 9, 2 | 2022-08-09 |
Optical element driving mechanism Grant 11,314,031 - Hu , et al. April 26, 2 | 2022-04-26 |
Establishing method for timing model Grant 11,256,838 - Liao , et al. February 22, 2 | 2022-02-22 |
Fixing device for clock tree and fixing method thereof Grant 11,182,524 - Kao , et al. November 23, 2 | 2021-11-23 |
Apparatus For Adjusting Skew Of Circuit Signal And Adjusting Method Thereof App 20210341962 - Wu; Tse-Wei ;   et al. | 2021-11-04 |
Establishing Method For Timing Model App 20210303767 - Liao; Hsin-Hsiung ;   et al. | 2021-09-30 |
Optical Element Driving Mechanism App 20210173171 - RYOO; Jungsuck ;   et al. | 2021-06-10 |
Optical Element Driving Mechanism App 20210149143 - HU; Chao-Chang ;   et al. | 2021-05-20 |
Optical Element Driving Mechanism App 20210132319 - HU; Chao-Chang ;   et al. | 2021-05-06 |
Optical System App 20210132360 - RYOO; Jungsuck ;   et al. | 2021-05-06 |
Optical System App 20210080681 - RYOO; Jungsuck ;   et al. | 2021-03-18 |
Circuit correction system and method for increasing coverage of scan test Grant 10,909,291 - Wu , et al. February 2, 2 | 2021-02-02 |
Optical System App 20200393637 - RYOO; Jungsuck ;   et al. | 2020-12-17 |
Circuit Correction System And Method For Increasing Coverage Of Scan Test App 20200380189 - WU; Tse-Wei ;   et al. | 2020-12-03 |
Timing model, timing model building method, and related top-level analysis method Grant 10,817,633 - Tsai , et al. October 27, 2 | 2020-10-27 |
Timing Model, Timing Model Building Method, And Related Top-level Analysis Method App 20200311218 - TSAI; Meng-Hsiu ;   et al. | 2020-10-01 |
Driving Mechanism App 20200271895 - FU; Kai-Jing ;   et al. | 2020-08-27 |
Driving Mechanism App 20200209520 - FU; Kai-Jing ;   et al. | 2020-07-02 |
Model-building method for building top interface logic model Grant 10,614,260 - Tsai , et al. | 2020-04-07 |
Model-building Method For Building Top Interface Logic Model App 20190294746 - TSAI; Meng-Hsiu ;   et al. | 2019-09-26 |
Model-building method and model-building system Grant 10,311,185 - Liao , et al. | 2019-06-04 |
Model-building Method And Model-building System App 20180330033 - LIAO; Hsin-Hsiung ;   et al. | 2018-11-15 |
Timing analysis method for digital circuit design and system thereof Grant 9,710,580 - Liao , et al. July 18, 2 | 2017-07-18 |
Timing Analysis Method For Digital Circuit Design And System Thereof App 20170011161 - Liao; Teng-Nan ;   et al. | 2017-01-12 |
Low leakage boundary scan device design and implementation Grant 9,246,488 - Tsai January 26, 2 | 2016-01-26 |
Low Leakage Boundary Scan Device Design and Implementation App 20130278287 - Tsai; Min-Hsiu | 2013-10-24 |
Through silicon via testing structure Grant 8,487,645 - Chang , et al. July 16, 2 | 2013-07-16 |
Low leakage boundary scan device design and implementation Grant 8,473,793 - Tsai June 25, 2 | 2013-06-25 |
Method for creating test clock domain during integrated circuit design, and associated computer readable medium Grant 8,468,407 - Chang , et al. June 18, 2 | 2013-06-18 |
Method For Creating Test Clock Domain During Integrated Circuit Design, And Associated Computer Readable Medium App 20120233513 - Chang; Ming-Tung ;   et al. | 2012-09-13 |
Through-silicon via testing structure App 20120012841 - Chang; Ming-Tung ;   et al. | 2012-01-19 |
Low leakage boundary scan device design and implementation App 20110307749 - Tsai; Min-Hsiu | 2011-12-15 |
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