Tsai; Kun-Chen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsai; Kun-Chen.The latest application filed is for "circuit board structure".

Company Profile

0.13.15

Tsai; Kun-Chen - Taoyuan TW
Tsai; Kun-Chen - Chiayi N/A TW
Tsai; Kun-Chen - Ping-Tung City TW
Tsai; Kun-Chen - Chiayi City TW
Tsai; Kun-Chen - Hsin-chu TW
Tsai; Kun-Chen - Chia-Yi TW
Tsai, Kun-Chen - Chia-Yi City TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuit board structure Grant 10,080,295 - Tsai September 18, 2	2018-09-18
Package structure Grant 8,786,108 - Tsai July 22, 2	2014-07-22
Electric door lock Grant 8,621,900 - Wu , et al. January 7, 2	2014-01-07
Lid for micro-electro-mechanical device and method for fabricating the same Grant 8,610,006 - Hsu , et al. December 17, 2	2013-12-17
Circuit Board Structure App 20130062100 - Tsai; Kun-Chen	2013-03-14
Lid, Fabricating Method Thereof, And Mems Package Made Thereby App 20130028450 - Cortese; Mario ; et al.	2013-01-31
Method of fabricating a circuit board structure Grant 8,302,297 - Tsai November 6, 2	2012-11-06
Package Structure App 20120049363 - Tsai; Kun-Chen	2012-03-01
Microelectromechanical System (mems) Carrier And Method Of Fabricating The Same App 20120032282 - Tsai; Kun-Chen	2012-02-09
Electric Door Lock App 20110259059 - WU; Rong-Faa ; et al.	2011-10-27
Circuit Board Structure And Fabrication Method Thereof App 20100187003 - Tsai; Kun-Chen	2010-07-29
Lid For Micro-electro-mechanical Device And Method For Fabricating The Same App 20100108345 - Hsu; Shih-Ping ; et al.	2010-05-06
Semiconductor package substrate having contact pad protective layer formed thereon Grant 7,485,970 - Hsu , et al. February 3, 2	2009-02-03
Method of fabricating electrical connection terminal of embedded chip App 20070130763 - Hsu; Shih-Ping ; et al.	2007-06-14
Method of fabricating electrical connection terminal of embedded chip Grant 7,174,631 - Hsu , et al. February 13, 2	2007-02-13
Semiconductor package substrate having contact pad protective layer formed thereon and method for fabricating the same App 20060226544 - Hsu; Shih-Ping ; et al.	2006-10-12
Semiconductor Package Substrate Having Contact Pad Protective Layer Formed Thereon And Method For Fabricating The Same App 20060223230 - Hsu; Shih-Ping ; et al.	2006-10-05
Semiconductor package substrate having contact pad protective layer formed thereon and method for fabricating the same Grant 7,081,402 - Hsu , et al. July 25, 2	2006-07-25
Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same App 20060157852 - Hsu; Shih-Ping ; et al.	2006-07-20
Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same Grant 7,012,019 - Hsu , et al. March 14, 2	2006-03-14
Electrical connection terminal of embedded chip and method for fabricating the same App 20050224976 - Hsu, Shih-Ping ; et al.	2005-10-13
Circuit barrier structure of semiconductor packaging substrate and method for fabricating the same App 20050082672 - Hsu, Shih-Ping ; et al.	2005-04-21
Semiconductor package substrate having contact pad protective layer formed thereon and method for fabricating the same App 20050037601 - Hsu, Shih-Ping ; et al.	2005-02-17
Door lock Grant 6,615,630 - Wu , et al. September 9, 2	2003-09-09
Door lock App 20020066297 - Wu, Rong-Faa ; et al.	2002-06-06

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.