Tsai; Jung-Hsun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Tsai; Jung-Hsun.The latest application filed is for "method and apparatus for forming self-aligned via with selectively deposited etching stop layer".

Company Profile

3.8.10

Tsai; Jung-Hsun - Hsin-Chu TW
Tsai; Jung-Hsun - Taoyuan City TW
Tsai; Jung-Hsun - Taoyuan TW

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Forming interlayer dielectric material by spin-on metal oxide deposition Grant 11,049,811 - Teng , et al. June 29, 2	2021-06-29
Method and Apparatus for Forming Self-Aligned Via with Selectively Deposited Etching Stop Layer App 20210098362 - Wu; Yung-Hsu ; et al.	2021-04-01
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Grant 10,867,913 - Wu , et al. December 15, 2	2020-12-15
Forming Interlayer Dielectric Material by Spin-On Metal Oxide Deposition App 20190131240 - Teng; Chi-Lin ; et al.	2019-05-02
Forming interlayer dielectric material by spin-on metal oxide deposition Grant 10,163,797 - Teng , et al. Dec	2018-12-25
Semiconductor device structure Grant 10,090,245 - Cheng , et al. October 2, 2	2018-10-02
Method And Apparatus For Forming Self-aligned Via With Selectively Deposited Etching Stop Layer App 20180211911 - Wu; Yung-Hsu ; et al.	2018-07-26
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Grant 9,922,927 - Wu , et al. March 20, 2	2018-03-20
Self-Aligned Interconnection Structure and Method App 20180076132 - Tsai; Jung-Hsun ; et al.	2018-03-15
Semiconductor Device Structure App 20180033730 - CHENG; Kai-Fang ; et al.	2018-02-01
Self-aligned interconnection structure and method Grant 9,818,690 - Tsai , et al. November 14, 2	2017-11-14
Semiconductor device structure and method for forming the same Grant 9,799,603 - Cheng , et al. October 24, 2	2017-10-24
Method And Apparatus For Forming Self-aligned Via With Selectively Deposited Etching Stop Layer App 20170256486 - Wu; Yung-Hsu ; et al.	2017-09-07
Semiconductor Device Structure And Method For Forming The Same App 20170213791 - CHENG; Kai-Fang ; et al.	2017-07-27
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Grant 9,659,864 - Wu , et al. May 23, 2	2017-05-23
Self-Aligned Interconnection Structure and Method App 20170125340 - Tsai; Jung-Hsun ; et al.	2017-05-04
Method And Apparatus For Forming Self-aligned Via With Selectively Deposited Etching Stop Layer App 20170110397 - Wu; Yung-Hsu ; et al.	2017-04-20
Forming Interlayer Dielectric Material By Spin-on Metal Oxide Deposition App 20170103949 - Teng; Chi-Lin ; et al.	2017-04-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.