Tsai; Han-Yung
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tsai; Han-Yung.The latest application filed is for "fabricating method of oxide layer within peripheral circuit region".
- Tsai; Han-Yung - Tainan TW
- Tsai; Han-Yung - Tainan City TW
| Patent | Date |
|---|---|
| Method for fabricating semiconductor device Grant 10,903,328 - Chen , et al. January 26, 2 | 2021-01-26 |
| Fabricating method of oxide layer within peripheral circuit region Grant 10,535,664 - Chen , et al. Ja | 2020-01-14 |
| Fabricating Method Of Oxide Layer Within Peripheral Circuit Region App 20190363093 - Chen; Po-Chun ; et al. | 2019-11-28 |
| Method For Fabricating Semiconductor Device App 20190280095 - Chen; Po-Chun ; et al. | 2019-09-12 |
| Memory devices and method of manufacturing the same Grant 10,332,888 - Liu , et al. | 2019-06-25 |
| Memory Devices And Method Of Manufacturing The Same App 20190148382 - Liu; Chih-Chien ; et al. | 2019-05-16 |
| Semiconductor structure Grant 10,249,706 - Chang , et al. | 2019-04-02 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 