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Three-dimensional stacking structure
Grant 10,777,534 - Huang , et al. Sept | 2020-09-15 |
Package structure having magnetic bonding between substrates
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Package Structure And Method For Forming The Same
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Three-dimensional Stacking Structure
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Three-dimensional stacking structure and manufacturing method thereof
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RF seal ring structure
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RF seal ring structure
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Self-aligned process for a stacked gate RF MOSFET device
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Lossless microstrip line in CMOS process
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Structure to reduce the degradation of the Q value of an inductor caused by via resistance
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Lossless microstrip line in CMOS process
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Self-aligned process for a stacked gate RF MOSFET device
App 20030008450 - Tsai, Chaochieh ; et al. | 2003-01-09 |
Self-aligned process for a stacked gate RF MOSFET device
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High Q inductor with Cu damascene via/trench etching simultaneous module
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Method to reduce a reverse narrow channel effect for MOSFET devices
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Process of making CMOS device structure having an anti-SCE block implant
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Process for manufacturing a single asymmetric pocket implant
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Ti-rich TiN insertion layer for suppression of bridging during a salicide procedure
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Silicon and arsenic double implanted pre-amorphization process for salicide technology
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Germanium and arsenic double implanted pre-amorphization process for salicide technology
Grant 6,030,863 - Chang , et al. February 29, 2 | 2000-02-29 |
CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation
Grant 5,757,045 - Tsai , et al. May 26, 1 | 1998-05-26 |
Method of fabricating MOSFET devices
Grant 5,702,972 - Tsai , et al. December 30, 1 | 1997-12-30 |
MOS device structure and integration method
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Isolation trench with a rounded top edge using an etch buffer layer
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CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process
Grant 5,668,024 - Tsai , et al. September 16, 1 | 1997-09-16 |
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