Tsai; Chao-Chieh
Patent Applications and Registrations
Patent applications and USPTO patent grants for Tsai; Chao-Chieh.The latest application filed is for "rf seal ring structure".
- Tsai; Chao-Chieh - Cupertino CA
- Tsai; Chao Chieh - Hsin Chu TW
- Tsai, Chao Chieh - Hsinchu TW
- Tsai, Chao-Chieh - Hsih-chu TW
- Tsai; Chao Chieh - Taichung TW
- Tsai; Chao-Chieh - Shin-Chu TW
| Patent | Date |
|---|---|
| Seal ring structure for radio frequency integrated circuits Grant RE41,668 - Tsai , et al. September 14, 2 | 2010-09-14 |
| RF seal ring structure Grant 7,265,438 - Tsai , et al. September 4, 2 | 2007-09-04 |
| Lossless co-planar wave guide in CMOS process Grant 7,081,648 - Tsai July 25, 2 | 2006-07-25 |
| High f.sub.MAX deep submicron MOSFET Grant 7,061,056 - Tsai , et al. June 13, 2 | 2006-06-13 |
| Seal ring structure for radio frequency integrated circuits Grant 6,967,392 - Tsai , et al. November 22, 2 | 2005-11-22 |
| RF seal ring structure App 20050248025 - Tsai, Chao Chieh ; et al. | 2005-11-10 |
| High fMAX deep submicron MOSFET App 20040018673 - Tsai, Chao-Chieh ; et al. | 2004-01-29 |
| Chip antenna with a shielding layer Grant 6,646,328 - Tsai November 11, 2 | 2003-11-11 |
| High fMAX deep submicron MOSFET Grant 6,613,623 - Tsai , et al. September 2, 2 | 2003-09-02 |
| Chip-antenna apparatus and method App 20030132430 - Tsai, Chao Chieh | 2003-07-17 |
| Seal ring structure for radio frequency integrated circuits App 20030122235 - Tsai, Chao-Chieh ; et al. | 2003-07-03 |
| Novel structure to reduce the degradation of the Q value of an inductor caused by via resistance App 20030076209 - Tsai, Chao Chieh ; et al. | 2003-04-24 |
| Metal fuse in copper dual damascene Grant 6,521,971 - Tsai February 18, 2 | 2003-02-18 |
| Salicide integration process App 20020192932 - Tsai, Chao-Chieh ; et al. | 2002-12-19 |
| Lossless co-planar wave guide in CMOS process App 20020168871 - Tsai, Chao Chieh | 2002-11-14 |
| Method for forming anchored bond pads in semiconductor devices and devices formed App 20020068385 - Ma, Ssu-Pin ; et al. | 2002-06-06 |
| High Fmax RF MOSFET with embedded stack gate Grant 6,376,351 - Tsai April 23, 2 | 2002-04-23 |
| Metal fuse in copper dual damascene App 20010054745 - Tsai, Chao-Chieh | 2001-12-27 |
| Method for fabricating raised source/drain structures Grant 6,303,448 - Chang , et al. October 16, 2 | 2001-10-16 |
| Method to form a high Q inductor Grant 6,258,688 - Tsai July 10, 2 | 2001-07-10 |
| STI process Grant 6,245,637 - Tsai June 12, 2 | 2001-06-12 |
| Method to fabricate high Q inductor by redistribution layer when flip-chip package is employed Grant 6,180,445 - Tsai January 30, 2 | 2001-01-30 |
| Borderless contact Grant 6,083,824 - Tsai , et al. July 4, 2 | 2000-07-04 |
| Dual damascene interconnect process with borderless contact Grant 6,020,255 - Tsai , et al. February 1, 2 | 2000-02-01 |
| Recessed structure for shallow trench isolation and salicide processes Grant 5,982,017 - Wu , et al. November 9, 1 | 1999-11-09 |
| Recessed structure for shallow trench isolation and salicide process Grant 5,891,771 - Wu , et al. April 6, 1 | 1999-04-06 |
| Method for forming high contrast alignment marks Grant 5,858,854 - Tsai , et al. January 12, 1 | 1999-01-12 |
| Method of salicidation for deep quarter micron LDD MOSFET devices Grant 5,648,287 - Tsai , et al. July 15, 1 | 1997-07-15 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 