Trombley; Michael R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Trombley; Michael R..The latest application filed is for "memory access alignment in a double data rate ('ddr') system".

Company Profile

0.27.26

Trombley; Michael R. - Cary NC
Trombley; Michael R. - Carey NC US
Trombley; Michael R. - Rochester MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory access alignment in a double data rate (`DDR`) system Grant 9,436,388 - Jenkins , et al. September 6, 2	2016-09-06
Memory Access Alignment In A Double Data Rate ('ddr') System App 20160216897 - JENKINS; STEVEN K. ; et al.	2016-07-28
Memory access alignment in a double data rate (`DDR`) system Grant 9,343,123 - Jenkins , et al. May 17, 2	2016-05-17
System for error decoding with retries and associated methods Grant 9,128,868 - Lastras-Montano , et al. September 8, 2	2015-09-08
Memory Access Alignment In A Double Data Rate ('ddr') System App 20140379979 - JENKINS; STEVEN K. ; et al.	2014-12-25
Memory access alignment in a double data rate (`DDR`) system Grant 8,902,683 - Jenkins , et al. December 2, 2	2014-12-02
Memory Access Alignment In A Double Data Rate ('ddr') System App 20130346686 - JENKINS; STEVEN K. ; et al.	2013-12-26
Memory access alignment in a double data rate (`DDR`) system Grant 8,547,760 - Jenkins , et al. October 1, 2	2013-10-01
Error correcting code protected quasi-static bit communication on a high-speed bus Grant 8,516,338 - Buchmann , et al. August 20, 2	2013-08-20
Memory Access Alignment In A Double Data Rate ('DDR') System App 20130003475 - Jenkins; Steven K. ; et al.	2013-01-03
Error Correcting Code Protected Quasi-static Bit Communication On A High-speed Bus App 20120272119 - Buchmann; Peter ; et al.	2012-10-25
Cascade interconnect memory system with enhanced reliability Grant 8,245,105 - Dell , et al. August 14, 2	2012-08-14
Error correcting code protected quasi-static bit communication on a high-speed bus Grant 8,234,540 - Buchmann , et al. July 31, 2	2012-07-31
System to improve error correction using variable latency and associated methods Grant 8,181,094 - Lastras-Montano , et al. May 15, 2	2012-05-15
System to improve miscorrection rates in error control code through buffering and associated methods Grant 8,176,391 - Baysah , et al. May 8, 2	2012-05-08
Power-on initialization and test for a cascade interconnect memory system Grant 8,139,430 - Buchmann , et al. March 20, 2	2012-03-20
Systems and methods for selectively closing pages in a memory Grant 8,140,825 - Balakrishnan , et al. March 20, 2	2012-03-20
Structure for reducing latency associated with read operations in a memory system Grant 8,140,803 - Allen, Jr. , et al. March 20, 2	2012-03-20
Methods, systems, and computer program products for dynamic selective memory mirroring Grant 8,099,570 - O'Connor , et al. January 17, 2	2012-01-17
Structure for handling data access Grant 8,032,713 - Allen, Jr. , et al. October 4, 2	2011-10-04
Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode Grant 8,028,257 - Allen, Jr. , et al. September 27, 2	2011-09-27
Balanced bandwidth utilization Grant 7,944,931 - Bass , et al. May 17, 2	2011-05-17
Structure for handling data requests Grant 7,937,533 - Allen, Jr. , et al. May 3, 2	2011-05-03
Error control coding methods for memories with subline accesses Grant 7,895,502 - Han , et al. February 22, 2	2011-02-22
System to Improve Miscorrection Rates in Error Control Code Through Buffering and Associated Methods App 20100299576 - Baysah; Irving G. ; et al.	2010-11-25
System to Improve Error Correction Using Variable Latency and Associated Methods App 20100293438 - Lastras-Montano; Luis A. ; et al.	2010-11-18
System for Error Decoding with Retries and Associated Methods App 20100287436 - Lastras-Montano; Luis A. ; et al.	2010-11-11
Systems and Methods for Selectively Closing Pages in a Memory App 20100037034 - Balakrishnan; Ganesh ; et al.	2010-02-11
Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode Grant 7,660,952 - Allen, Jr. , et al. February 9, 2	2010-02-09
Method and apparatus for reducing latency associated with read operations in a memory system Grant 7,657,771 - Allen, Jr. , et al. February 2, 2	2010-02-02
Cascade Interconnect Memory System With Enhanced Reliability App 20100005366 - Dell; Timothy J. ; et al.	2010-01-07
Error Correcting Code Protected Quasi-static Bit Communication On A High-speed Bus App 20100005365 - Buchmann; Peter ; et al.	2010-01-07
Automatic Read Data Flow Control In A Cascade Interconnect Memory System App 20100005206 - Hnatko; Steven J. ; et al.	2010-01-07
Power-on Initialization And Test For A Cascade Interconnect Memory System App 20100005281 - Buchmann; Peter L. ; et al.	2010-01-07
Enhancing Bus Efficiency In A Memory System App 20100005214 - Trombley; Michael R. ; et al.	2010-01-07
Providing A Variable Frame Format Protocol In A Cascade Interconnected Memory System App 20100005212 - Gower; Kevin C. ; et al.	2010-01-07
Arrangements for Operating In-Line Memory Module Configurations App 20090276559 - Allen, JR.; James J. ; et al.	2009-11-05
Methods, Systems, And Computer Program Products For Dynamic Selective Memory Mirroring App 20090216985 - O'Connor; James A. ; et al.	2009-08-27
Structure For Handling Data Requests App 20090150572 - ALLEN, JR.; JAMES J. ; et al.	2009-06-11
Structure For Handling Data Access App 20090150618 - Allen, JR.; James J. ; et al.	2009-06-11
Memory System With Apparatus And Method To Enable Balanced Bandwidth Utilization App 20080240110 - Bass; Brian M. ; et al.	2008-10-02
Data Bus Bandwidth Scheduling In An Fbdimm Memory System Operating In Variable Latency Mode App 20080215832 - Allen; James J. ; et al.	2008-09-04
Structure For Data Bus Bandwidth Scheduling In An Fbdimm Memory System Operating In Variable Latency Mode App 20080215783 - Allen; James J. ; et al.	2008-09-04
Structure For Reducing Latency Associated With Read Operations In A Memory System App 20080209095 - ALLEN; JAMES J. ; et al.	2008-08-28
Method And Apparatus For Reducing Latency Associated With Read Operations In A Memory System App 20080168293 - ALLEN; James J. ; et al.	2008-07-10
Error Control Coding Methods For Memories With Subline Accesses App 20080168329 - Han; Junsheng ; et al.	2008-07-10
Memory system with apparatus and method to enable balanced bandwidth utilization Grant 7,286,543 - Bass , et al. October 23, 2	2007-10-23
Memory system with apparatus and method to enable balanced bandwidth utilization App 20030161315 - Bass, Brian M. ; et al.	2003-08-28
Independent control of DMA and I/O resources for mixed-endian computing systems Grant 5,781,763 - Beukema , et al. July 14, 1	1998-07-14
Variable stage entry/exit instruction pipeline Grant 5,471,626 - Carnevale , et al. November 28, 1	1995-11-28

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