Trocino; Michael R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Trocino; Michael R..The latest application filed is for "processing system with interspersed processors dma-fifo".

Company Profile

13.25.30

Trocino; Michael R. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Processing System With Interspersed Processors DMA-FIFO App 20210326193 - Dobbs; Carl S. ; et al.	2021-10-21
Memory-network Processor With Programmable Optimizations App 20210208895 - Doerr; Michael B. ; et al.	2021-07-08
Processing system with interspersed processors DMA-FIFO Grant 11,030,023 - Dobbs , et al. June 8, 2	2021-06-08
Memory-network processor with programmable optimizations Grant 11,016,779 - Doerr , et al. May 25, 2	2021-05-25
Memory Network Processor App 20210034566 - Dobbs; Carl S. ; et al.	2021-02-04
Processing system with interspersed processors with multi-layer interconnect Grant 10,838,787 - Dobbs , et al. November 17, 2	2020-11-17
Multiprocessor System With Improved Secondary Interconnection Network App 20200341914 - Dobbs; Carl S. ; et al.	2020-10-29
Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric App 20200302090 - Doerr; Michael B. ; et al.	2020-09-24
Multiprocessor system with improved secondary interconnection network Grant 10,747,689 - Dobbs , et al. A	2020-08-18
Memory network processor Grant 10,747,709 - Dobbs , et al. A	2020-08-18
Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric Grant 10,685,143 - Doerr , et al.	2020-06-16
Processing System With Interspersed Processors With Multi-layer Interconnect App 20200117521 - Dobbs; Carl S. ; et al.	2020-04-16
Processing system with interspersed processors with multi-layer interconnection Grant 10,521,285 - Dobbs , et al. Dec	2019-12-31
Memory-Network Processor with Programmable Optimizations App 20190369990 - Doerr; Michael B. ; et al.	2019-12-05
Processing System With Interspersed Processors With Multi-Layer Interconnection App 20190155666 - Dobbs; Carl S. ; et al.	2019-05-23
Multiprocessor System with Improved Secondary Interconnection Network App 20190155761 - Dobbs; Carl S. ; et al.	2019-05-23
Memory Network Processor App 20190138492 - Dobbs; Carl S. ; et al.	2019-05-09
Processing system with interspersed processors with multi-layer interconnection Grant 10,185,608 - Dobbs , et al. Ja	2019-01-22
Multiprocessor system with improved secondary interconnection network Grant 10,185,672 - Dobbs , et al. Ja	2019-01-22
Secure Boot Sequence for Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric App 20180276416 - Doerr; Michael B. ; et al.	2018-09-27
Processing System With Interspersed Processors With Multi-Layer Interconnection App 20180267846 - Dobbs; Carl S. ; et al.	2018-09-20
Clock distribution network for multi-frequency multi-processor systems Grant 10,007,293 - Dobbs , et al. June 26, 2	2018-06-26
Secure boot sequence for selectively disabling configurable communication paths of a multiprocessor fabric Grant 10,007,806 - Doerr , et al. June 26, 2	2018-06-26
Processing system with interspersed processors with multi-layer interconnection Grant 9,990,241 - Dobbs , et al. June 5, 2	2018-06-05
Processing System With Interspersed Processors With Multi-Layer Interconnection App 20170286196 - Dobbs; Carl S. ; et al.	2017-10-05
Processing system with interspersed processors with multi-layer interconnection Grant 9,720,867 - Dobbs , et al. August 1, 2	2017-08-01
Multiprocessor System With Improved Secondary Interconnection Network App 20170161214 - Dobbs; Carl S. ; et al.	2017-06-08
Multiprocessor system with improved secondary interconnection network Grant 9,612,984 - Dobbs , et al. April 4, 2	2017-04-04
Clock Distribution Network For Multi-frequency Multi-processor Systems App 20160370823 - Dobbs; Carl S. ; et al.	2016-12-22
Processing System With Interspersed Processors With Multi-Layer Interconnection App 20160335218 - Dobbs; Carl S. ; et al.	2016-11-17
Processing System With Interspersed Processors DMA-FIFO App 20160335207 - Dobbs; Carl S. ; et al.	2016-11-17
Memory-network Processor With Programmable Optimizations App 20160328231 - Doerr; Michael B. ; et al.	2016-11-10
Clock distribution network for multi-frequency multi-processor systems Grant 9,450,590 - Dobbs , et al. September 20, 2	2016-09-20
Processing system with interspersed processors with multi-layer interconnect Grant 9,430,422 - Dobbs , et al. August 30, 2	2016-08-30
Memory-network processor with programmable optimizations Grant 9,430,369 - Doerr , et al. August 30, 2	2016-08-30
Processing system with interspersed processors DMA-FIFO Grant 9,424,213 - Dobbs , et al. August 23, 2	2016-08-23
Multiprocessor fabric having configurable communication that is selectively disabled for secure processing Grant 9,424,441 - Doerr , et al. August 23, 2	2016-08-23
Secure Boot Sequence for Selectively Disabling Configurable Communication Paths of a Multiprocessor Fabric App 20160232357 - Doerr; Michael B. ; et al.	2016-08-11
Multiprocessor System With Improved Secondary Interconnection Network App 20160162424 - Dobbs; Carl S. ; et al.	2016-06-09
Automatic selection of on-chip clock in synchronous digital systems Grant 9,325,329 - Dobbs , et al. April 26, 2	2016-04-26
Multiprocessor system with improved secondary interconnection network Grant 9,292,464 - Dobbs , et al. March 22, 2	2016-03-22
Multi-frequency clock skew control for inter-chip communication in synchronous digital systems Grant 9,154,142 - Dobbs , et al. October 6, 2	2015-10-06
Multi-frequency Clock Skew Control For Inter-chip Communication In Synchronous Digital Systems App 20150162920 - Dobbs; Carl S. ; et al.	2015-06-11
Multi-frequency clock skew control for inter-chip communication in synchronous digital systems Grant 8,963,599 - Dobbs , et al. February 24, 2	2015-02-24
Multiprocessor Fabric Having Configurable Communication that is Selectively Disabled for Secure Processing App 20150026451 - Doerr; Michael B. ; et al.	2015-01-22
Memory-network Processor With Programmable Optimizations App 20140351551 - Doerr; Michael B. ; et al.	2014-11-27
Method and system for disabling communication paths in a multiprocessor fabric by setting register values to disable the communication paths specified by a configuration Grant 8,880,866 - Doerr , et al. November 4, 2	2014-11-04
Multi-frequency Clock Skew Control For Inter-chip Communication In Synchronous Digital Systems App 20140167825 - Dobbs; Carl S. ; et al.	2014-06-19
Automatic Selection Of On-chip Clock In Synchronous Digital Systems App 20140173324 - Dobbs; Carl S. ; et al.	2014-06-19
Multiprocessor System With Improved Secondary Interconnection Network App 20140173161 - Dobbs; Carl S. ; et al.	2014-06-19
Clock Distribution Network For Multi-frequency Multi-processor Systems App 20140173321 - Dobbs; Carl S. ; et al.	2014-06-19
Processing System With Interspersed Processors DMA-FIFO App 20140143470 - Dobbs; Carl S. ; et al.	2014-05-22
Processing System With Interspersed Processors With Multi-Layer Interconnect App 20140143520 - Dobbs; Carl S. ; et al.	2014-05-22
Disabling Communication in a Multiprocessor System App 20120137119 - Doerr; Michael B. ; et al.	2012-05-31

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